Lab

Lab 5 - EE 421L

Authored by Sharyn Miyaji,

Wednesday, October 5, 2016

Pre-Lab Work

For Pre-Lab, we needed to go through Tutorial 3 in preparation for this lab. In the tutorial, an inverter is created using a NMOS and PMOS and then tested out.

Lab Work

Creating a 12u/6u Inverter

First, a pmos4, nmos4, vdd, and gnd are added to the schematic with vdd attached to the source of the PMOS and ground attached to the source of the NMOS. The width of the PMOS is 6um and the length is 600nm, and the width of the NMOS is 6um and the length is 600nm. Attach the body of the NMOS and PMOS to its own source terminal. Then attach the gates of both NMOS and PMOS together with an input pin A and attach their drains together with an output pin Ai. Lastly, Check and Save.

Schematic

Convert the schematic into a symbol and use note (shift + N) to keep track of the widths of the PMOS and NMOS.

Symbol

Create a layout with an ntap, ptap, m1_poly, pmos, and nmos. The size of the NMOS and PMOS are the same as the ones in the schematic. Then connect the poly and one side of the metal1 layers of the NMOS and PMOS. The path of the poly is also connected to the m1_poly. After connect the other side of the metal1 of the NMOS to the metal1 of the ntap and the other side of the metal1 of the PMOS to the metal1 of the ptap. Lastly, add metal1 pins to the ntap as vdd!, ptap as gnd!, m1_poly as pin A, and path between the NMOS and PMOS as Ai. Then DRC the layout, extract it, and LVS the schematic and extracted layout of the inverter.

Layout and Extracted Layout

DRC and LVS

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%205/12u_6u_inverter_LVS_window.JPG

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%205/12u_6u_inverter_LVS_netlist.JPG

Creating a 48u/24u inverter

Since the same schematic as the 12u/6u inverter is being used for the 48u/24u inverter, the file of the 12u/6u inverter can be copied and renamed. When the file is copied over, change the multiplier of both the NMOS and PMOS from 1 to 4. Once that is done, Check and Save the schematic.

Schematic

Again, convert the schematic into a symbol and use note (shift + N) to keep track of the widths of the PMOS and NMOS.

Symbol

Create a layout with an ntap, ptap, m1_poly, pmos, and nmos. The size and multipliers of the NMOS and PMOS are the same as the ones in the schematic. Then connect each of the poly layers of the NMOS and PMOS that are adjacent to each other. Connect the second and fourth metal1 layer of the NMOS and PMOS together. Connect the first, third, and fifth metal1 of the NMOS to the metal1 of the ntap, and again with the PMOS except it is connected to the ptap. The m1_poly is connected to all of the poly rectangles using the poly layer. Lastly, add metal1 pins to the ntap as vdd!, ptap as gnd!, m1_poly as pin A, and path between the NMOS and PMOS as Ai. Then DRC the layout, extract it, and LVS the schematic and extracted layout of the inverter.

Layout and Extracted Layout

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%205/48u_24u_inverter_layout.JPG

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%205/48u_24u_inverter_extracted.JPG

DRC and LVS

Simulations with Different Loads

Using a 12u/6u inverter:

Capacitor Load Value	Schematic	Simulation
100fF
1pF
10pF
100pF

Using a 48u/24u inverter:

Capacitor Load Value	Schematic	Simulation
100fF
1pF
10pF
100pF

Based on the simulations above, the time delay increases as the value of the capacitor increases. When the inverter is multiplied by 4, the time delay of the simulations are shorter than the ones with the inverter multiplied by 1. The larger inverter is faster because the resistance is smaller causing it to charge and discharge faster; therefore, there is more current flowing in, flowing out, and being stored.

UltraSimulations

Again, simulate the schematics above, except change the simulator to UltraSim in the Choosing Simulator/Directory/Host instead of Spectre. UltraSim simulates the schematic faster.

Using 12u/6u inverter: