Lab

Lab 4 - EE 421L

Authored by Sharyn Miyaji,

Email: miyajis@unlv.nevada.edu

Wednesday, September 28, 2016

Pre Lab Work

For Pre Lab, we needed to go through Tutorial 2 in preparation for this lab. When creating the NMOS and PMOS device as done in Tutorial 2, the body of the NMOS (substrate) has to be connected to ground (gnd!) and the body of the PMOS has to be connected to the voltage source (vdd!) as seen below.

NMOS

Layout	Schematic	Symbol

PMOS

Layout	Schematic	Symbol

Lab Work

Simulations

1. Using the symbol of the NMOS (6u/600n) that was created in the prelab (Tutorial 2), we connect the source of the NMOS to ground, the gate of the NMOS to a voltage source of VGS, and the drain of the NMOS to separate voltage source of 1 volts to plot an ID vs. VDS curve of an NMOS device. The VGS is set from 0 to 5 volts in 1 volts steps and VDS is varying from 0 to 5 volts in 1 mV steps. Before plotting the IV curve, select the drain current for the simulations. In the simulation, each of the lines represents the drain current at the different voltage from the drain to the source starting at 0 volts to 5 volts.

2. To plot an ID vs. VGS curve of an NMOS (6u/600n) device, the same schematic is used as the ID vs. VDS, but VDS is changed to 100 mV instead of 1 volts and VGS will be varying from 0 to 2 volts in 1 mV steps. In the simulation, VGS is greater than the threshold voltage, which causes the current to rise.

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%204/Schematic2.JPG

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%204/Simulation2.JPG

3. To plot an ID vs. VSD curve using a PMOS device (12u/600n) symbol, add the PMOS that was created from Tutorial 2 and 3 DC voltage sources. The gate of the PMOS is connected to the negative terminal of the voltage source that is equal to VSG. The positive terminal of the VSG is connected to the source of the PMOS and positive terminals of the two other voltage sources, which are set to 0 volts and 5 volts and represents vdd!. The body is connected back to the source of the PMOS and the drain of the PMOS is connected to the negative terminal of the voltage source at 0 volts, and the negative terminal of the voltage source of 5 volts is connected to ground. When simulating, VSG is set to 0 to 5 volts in 1 volt steps, and VSD is varing from 0 to 5 volts in 1 mV. Again, the lines in the simulation represents drain current when VSG increases in increments of 1 volts starting at 0 volts.

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%204/Schematic3.JPG

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%204/Simulation3.JPG

4. To plot a ID vs. VSG curve of a PMOS device (12u/600n), the same schematic previously is used, except VSD is set to 100 mV and VSG is varying from 0 to 2 volts in 1 mV steps. The simulation is a representation of the amount of VSG needed in order for the drain current to rise.

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%204/Schematic4http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%204/Schematic3.JPG.JPG

http://cmosedu.com/jbaker/courses/ee421L/f16/students/miyajis/Lab%204/Simulation4.JPG

NMOS Device with Probe Pads

Before attaching the probe pads to the NMOS device, the NMOS created earlier must be modified to where the body of is a pin instead of it being connected to ground. Once those changes are made, then the attach a probe pad to each of the terminals in the NMOS device in layout and schematic as shown below.

Layout