Lab 6 - EE 421L: Digital Integrated Circuit
Design Laboratory
·
Back-up all of your work from the lab and the course.
·
Go through Cadence Tutorial 4 seen here.
·
Read through the lab in its entirety before starting to work on it
Post-Lab Scope
·
Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a
2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)
o Create layout
and symbol views for these gates showing that the cells DRC and LVS
without errors
§ ensure that
your symbol views are the commonly used symbols (not boxes!) for these gates
with your initials in the middle of the symbol
§ ensure all
layouts in this lab use standard cell frames that snap together end-to-end
for routing vdd! and gnd!
§ use
a standard cell height taller than you need for these gates so that
it can be used for more complicated layouts in the future
§ ensure gate
inputs, outputs, vdd!, and gnd! are all routed on
metal1
o Use cell names
that include your initials and the current year/semester, e.g. NAND_jb_f19 (if
it were fall 2019)
o Using Spectre simulate the logical operation of the gates for all
4 possible inputs (00, 01, 10, and 11)
§ comment on how
timing of the input pulses can cause glitches in the output of a gate
o Your html lab
report should detail each of these efforts
o Below shows
(click for a larger image): 1) schematic of a 2-input NAND gate, 2) schematic
of a 2-input XOR gate, 3) simulation schematic, 4) example pulse statement to
generate a digital input, and 5) simulating the operation of the gates for all
4 possible inputs.
- Using these
gates, draft the schematic of the full adder seen below
- Create
a symbol for this full-adder (example)
- Simulate,
using Spectre, the operation of the
full-adder using this symbol
- Layout the
full-adder by placing the 5 gates end-to-end so that vdd!
and gnd! are routed
- full-adder
inputs and outputs can be on metal2 but not metal3
- The cells used to
generate the images used on this webpage are found in lab6.zip
Post-Lab:
Below are the post-lab deliverables.
Below in
figure 1 you will see the schematic, layout, extracted and symbol views of the
2-input NAND gate.
Figure 1
Below in
figure 2 you will see the successful DRC and LVS of the 2-input NAND gate.
Figure 2
Below in
figure 3 you will see the simulation results of the 2-input NAND gate followed
by the truth table.
Figure 3
NAND Table
As
can be seen, there are glitches also known as combinational logic hazards that
occur during on/off transitions and switching overlap. These occur because of the propagation delay
through a device which can vary from gate to gate depending on the design of
the MOSFET. These glitches will become
more apparent with more intricate logic design.
Below in
figure 4 you will see the schematic, layout, extracted and symbol views of the
2-input XOR gate.
Figure 4
Below in
figure 5 you will see the successful DRC and LVS of the 2-input XOR gate.
Figure 5
Below in
figure 6 you will see the simulation results of the 2-input XOR gate followed
by the truth table.
Figure 6
XOR Table
Again as you
can see the glitches are not in this simulation as the on/off transitions never
overlap.
Below in
figure 7 you will see the schematic, layout, extracted and symbol views of the
Full Adder.
Figure 7
Below in
figure 8 you will see the simulation results of the Full Adder followed by the
truth table.
Figure 8
Full Adder Table
As you can see
with a more complicated circuit the glitches become more apparent.
Conclusion
In conclusion Lab 6 served to provide knowledge in the
construction, design, and simulation of 2-input NAND and XOR gates as well as
the Full Adder.
My Lab 6 files can be found here to authenticate unique individual
experiments and designs.
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Baker’s Course Listings