The
following circuits with inputs (clk and in) will implement our D Flip Flop (D-FF) for our design.
CLOCK 1
Schematic: 
Symbol: 
Layout:
DRC: 
LVS: 
CLOCK 2:
Schematic:
Symbol: 
Layout:
DRC: 
LVS: 
Using
CLOCK we implement a Edge-Triggered D-FF from Fig. 13.22 (pg.387).
Edge-Triggered D-FF
Schematic:
Symbol:
Simulation:
We can see that Q and Q' both trigger on the rising edge of the CLOCK inputs (clk and in)
Layout:
DRC: 
LVS: 
We
create a 6-Bit NAND for our sequence
101011.
NAND GATE
Schematic: 
Symbol: 
Simulation: 
The
NAND Gate simulation shows that we can output a nand high (1) and a nand low (0).
Layout: 
DRC: 
LVS:
Finally
we create our DETECT circuit for sequence 101011 using our BUFFER, CLOCK, D-FF,
NAND circuits. DETECT
Schematic: 
Symbol: 
Simulation Schematic:
Simulation using 101011:
Simulation using: 110011 (
No Detect) 
Layout: The
final layout for this project is the Detector Circuit with output buffer. The layout was straightforward to do, and I basically instantiated six of the D-Flip Flop Layouts and instantiated them end to end as shown. Next, I connected all the clk inputs of the D-Flip Flops into one common connection using the metal 1 layer. Furthermore, I connected the D, Q, and Q' outputs into the 6-input NAND Gate. The last connection to do was to connect the "Z" output of the NAND Gate into the output buffer.
Below is a zoomed in version of the Detector Circuit Layout showing the NAND Gate and output buffer. Basically, all the poly connections from the flip flops are connected to the inputs of the NAND Gate. The output of the NAND gate is then connected to the input of the output buffer, and the "Detect" pin is then placed on the output of the buffer. 
DRC:
LVS: 
