Final Project - EE 421L

Authored by

11/30/2016

Final Project - Design a circuit that takes a serial input and detects (outputs a high logic signal called detect) the sequence 101011.

A buffer will be needed for the output of the DETECT before connecting to the padframe.

BUFFER
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The following circuits with inputs (clk and in) will implement our D Flip Flop (D-FF) for our design.

CLOCK 1
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CLOCK 2:
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Using CLOCK we implement a Edge-Triggered D-FF from Fig. 13.22 (pg.387).

Edge-Triggered D-FF
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Simulation:


We can see that Q and Q' both trigger on the rising edge of the CLOCK inputs (clk and in)

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We create a 6-Bit NAND for our sequence 101011.

NAND GATE
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  The NAND Gate simulation shows that we can output a nand high (1) and a nand low (0).

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Finally we create our DETECT circuit for sequence 101011 using our BUFFER, CLOCK, D-FF, NAND circuits.

DETECT
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Simulation Schematic:


Simulation using 101011:

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