Lab 6 - EE 421L
Note that this NAND gate uses 6u/0.6u MOSFETS for both NMOS and PMOS. Then, the symbol is created.
Next, we use the symbol to simulate our NAND gate and verify it works properly.
'Check and Save' to make sure the 'vdd' and NAND symbol do not overlap.
Making sure that the corresponding nmos and pmos models are added, simulation is perfromed.
Now that simulation matches our expected results, we can layout the NAND gate as seen below. Then, we can extract it.
DRC the layout to verify that any rule was violated.
Note that, since the metal1 connection between NMOS devices were not needed, I just removed it using Edit-> Hierarchy->Flatten to convert NMOS cells in rectangles.
For some reason, tutorial 4 shows 12u/0.6u PMOS devices in the layout. However, since 6u/0.6u PMOS devices were used in the schematics and simulations, and further in laboratory experiments, I laid out NAND gate with 6u/0.6u MOSFETS for both NMOS and PMOS. Moreover, I modified the previous layout in this prelab, so it matches the lab requirements (see below).
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Post Lab Report
Lab description: In this laboratory exercise, we were to draft the schematics and symbols, simulate, layout, and LVS a 2-input NAND gate, 2-input XOR gate, and a Full Adder.
I made use of my NAND cells created in the prelab, so I start by copying them to a new library called 'Lab6' and renamed it as NAND_ls_f15, per lab requirements. Again, the schematic, symbol, and layout are shown below. Note that I named the symbol as NAND_LS.
Next, the schematic for XOR gate is drafted as follows.
'Check and save' to ensure no connection errors in the schematic.
Now, the symbol is created and named as XOR_LS as seen below.
The XOR gate is laid out as shown below
However, according to the lab requirements, I modified the mayout and used a much higher standard cell height.
DRC to verify no rules were violated.
It is worth to mention that I had a hard time trying to interconnect the MOSFETs. At the end, I decided to make most of the connections in the n-well layer of the PMOS devices, so there is more space between NMOS and PMOS devices. Also, I used the metal2 layer to route over metal 1 layer and avoid overlapping. Finally, bigger ntap and ptap were used for vddd and gnd, repectively, connected to metal1 layer to avoid ground bouncing. Now, the extracted layout and corresponding LVS is shown below. The LVS (layout vs schematic)shows that both netlists matched.
Now, I can proceed with the simulation of the NAND gate, XOR gate, and inverter to verify that the following truth table is satistfied.
A | B | not A | AnandB | AxorB |
0 | 0 | 1 | 1 | 0 |
0 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 1 |
1 | 1 | 0 | 0 | 0 |
The inverter was copied from the previous lab 3 added to Lab6, per lab requirement. It was not indeed needed as part of the laboratory experiments.
Adding the corresponding NMOS and PMOS models, the simulation can then be performed
cin | a | b | s | cout |
0 | 0 | 0 | 0 | 0 |
0 | 0 | 1 | 1 | 0 |
0 | 1 | 0 | 1 | 0 |
0 | 1 | 1 | 0 | 1 |
1 | 0 | 0 | 1 | 0 |
1 | 0 | 1 | 0 | 1 |
1 | 1 | 0 | 0 | 1 |
1 | 1 | 1 | 1 | 1 |
As always, back up of this lab was saved on my flashdrive and Google Drive account. Additionally, all the cell used in this lab can be downloaded here
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