Lab 5 - EE 421L
The NMOS and PMOS length for both inverters is the same and equal to 600nm (0.6um).
The first inverter has a 12u/0.6u PMOS and 6u/0.6u NMOS in series as explained in Turtorial 3.
Input and output pins are called A and Ai respectively. Check and Save my schematic to ensure no errors were found.
Based on this, a symbol was created.
Now, similar to the previous step, I created a 48u/24u inverter. Based on the previous schematic, this can be accomplished by multiplying the width of both NMOS and PMOS by 4 (m=4) as seen below, left. A symbol was modeled as well (see below on the rigth).
As before, I check and save my work to make sure no errors were found.
2. Layout and LSV of 12u/6u and 48u/24u inverters
In this part of the lab, I layout both inverter schematicsand then performed LVS with the corresponding extracted view.
Layout and extracted view for the 12u/6u inverter are shown below. Notice that VDD and gnd are shown as global variables in lower case letters.
As always, DRC is done to to save the layout with no errors.
LVS of the extracted layout and schematic is performed to verify that both netlists match.
After that, layout and extracted view for the 48u/24u inverter are shown below
DRCing to show any rule was violated in the layout,
Again, LVS of extracted view and schematic is applied on the inverter to check the netlists match.
3. Simulation of 12u/6u and 48u/24u inverters for 100 fF, 1 pF, 10pF, and 100 pF loads
The next step in this lab was to simulate both inverters when VDD is 5v and carrying capacitive loads of 100 fF, 1 pF, 10pF, and 100 pF. Additionally, apart of using Spectre, UltraSim simulation was applied.
Before simulating, the models for the NMOS and PMOS had to be specified as follows.
The follwing table shows the schematics, Spectre simulations, and UltraSim simulations for all four different capacitive loads using the 12u/6u inverter.
| Schematic | Spectre Simulation | UltraSim simulation |
 |  |  |
 |  |  |
 |  |  |
 |  | |
From table, it is seen that my inverter works as expected, i.e. when the input goes from low to high voltage, the output goes from high to low voltage. However, this functions properly when the load is low. It can be observed that, when the load increases, the output takes longer to change from high to low voltage. This effect will be analysed later in this report. Now, let's simulate the 48u/24u inverter.
The following table shows the 48u/24u inverter schematics and simulations for all four capacitive loads.
| Schematic | Spectre Simulation | UltraSim Simulation |
 |  |  |
 |  |  |
 |  |  |
 |  |  |
From this table, it is seen again that this inverter works as expected same as the previous case. However, this inverter has a width that is 4 times bigger as the first one. That means that the width of the gate is 4 times larger, so resistance is lower. Then, the time delay, which is dependent on RC, decreases, as seen on both tables: time delay in48u/24u inverter is less than time delay in 12u/6u inverter. Moreover , for both tables, it is again observed that, as the load increases, it takes more time for the output to go from high to low voltage. This is due to, as the load increases, it takes more time to charge the capacitance, so RC delay increase. In other words, it takes more time for the output to reach a low voltage.
In conclusion, when comparing both inverters, the limitations on the first inverter start appearing when the load is 10 pF. On the other hand, these limitations appear when the load is 100 pF for the second inverter. Hence, the 48u/24u inverter has better performance thatn the 12u/6u inverter.
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As always, back up of this lab was saved on my flashdrive and Google Drive account. Additionally, the whole lab can be downloaded here
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