For Lab 3, we have to construct the layout of the DAC designed Lab 2 (my lab 2 report here).To begin the layout, a new library must be created, then the DAC schematic created in Lab 2 copied into it. Once that is complete, we can create a new layout cell view and begin the layout of the DAC using a resistor ladder network. The full library for lab 3 is shown below:
Layout of a 10k resistor:
To create a resistor of a certain value using the n-well, we must set the length and width of the n-well according to the process information from MOSIS. The sheet resistance of the n-well is 800 ohms per square. Thus, the total resistance of our n-well resistor will be 800 (L/W). But the minimum width according to MOSIS C5 process is 3.6um. However, we also need to keep in mind the grid is .15 um:
We must have the n-well line up on the .15um grid. So as in Tutorial 1, we can set the width to 4.5 um (divisible by .15), and adjust the length to be 56.1 (adjusted from 56 so it's divisible by .15).
After extracting the n-well resistor, we can check its value by zooming in on the left side of the extracted view:
The value is 10.21k, which is close enough to 10k for us.
Using this n-well resistor in the layout of the DAC:
To begin with, three resistors are instantiated to create the basic R-2R cell, which we can copy in an array of 9. Each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions. The bottom cell must be connected to the bottom resistor, then to ground. All input and output pins are on metal 1 (seen here for B0 and gnd!):
The entire DAC looks like this:
Now, we have to DRC, extract the layout, and perform the LVS.
The LVS was successful:
Finally, we can simulate the extracted view of the layout by going to our sim_10-bit DAC cell and selecting Setup -> Environment and adding the word "extracted" before "schematic in the window:
The simulation is as follows:
This simulation looks like it was successful, since it matches what was simulated with the schematic in Lab 2.
But just to be sure we are simulating the extracted view, we check by selecting Simulation -> Netlist -> Display and checking to see that it shows the simulation is really from the extracted view:
