Lab 8

Lab 8 - EE 421L

Authored by Shada Sharif,

Group: Stephanie Silic, Jared Hayes, Juan Buendia

sharifs@unlv.nevada.edu

30 November 2015

Pre-lab work:

Lab Description:

The lab is about generating a test chip layout that will be submitted to MOSIS for fabrication.

Lab Report will include:

A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
NAND and NOR gates using 6/0.6 NMOSs and PMOSs
An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad)

Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit

Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor)
A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)
Analog padframe with all the parts mentioned above.
Instructions for testing the chip.

Chip 1 Padframe:

The padframe shown below includes 8-bit UP/DOWN counter with a CLEAR, PMOS and NMOS, NAND and NOR gates, 31-stage ring oscillator as well as a voltage divider.
The padframe used is an analog padframe, which means that it has ESD protection. The main vdd of the padframe that is pin 40 shown be powered in order for the ESD protection to work.
Other part's vdds were shared when possible, and ground was shared between all the parts.
Buffers were added for the 31-stage ring oscillator, and for each output of the 8-bit counter.
Below shown the padframe with the DRC no error, as well as the LVS matching between the schematic and the extracted.

CLICK ON IMAGE TO ENLARGE

Testing Instructions:

For all the parts bellow pin<20> should always be connected to ground and pin<40> should always be connected to vdd.

The first thing to do before using the counter is to connect pin<8> to an external vdd so that the counter is powered.
Our counter is able to count UP/DOWN depending in the UP_in, which is pin<9> signal provided, when UP_in is high the counter counts up, and when UP_in is low the counter counts down.
For the counting to start happening user should input a clock signal to pin<10> that is CLK. Looking at Project report user can understand how the counter functions.
The CLEAR input is pin<11> and when it is high the output is cleared to 0, and when it is low the counter works as normal.
As for the 8 bit outputs we have

To power the ring oscillator connect vdd to a power supply and that is pin<24>.
The output of the oscillator can be observed from pin<25>.
The output of the oscillator has already been buffered on-chip so that the oscillator can handle a 20 pF off-chip load.
The testing of the oscillator driving the 20 pF load can also be seen in Project report.

Sample simulations for the nand and nor gates can be found in Project report, showing different inputs and the corresponding outputs.

To power the inverter's vdd connect pin<35> to a power supply.
The input of the inverter is shared again from pin<29> that was used for the NAND and NOR gates.
The output is measured from pin<34>.

The gate of the PMOS is connected to pin<17>.
The source of the PMOS is connected to pin<16>.
The drain of the PMOS is connected to pin<18>.
The body of the PMOS is connected to pin<19>.
In order to avoid body effects of the PMOS the body should be connected to vdd from the power supply. Otherwise, the characteristics of the PMOS will vary like the Vth voltage.

The gate of the NMOS is connected to pin<23>.
The source of the NMOS is connected to pin<22>.
The drain of the NMOS is connected to pin<21>.
The body of the NMOS is connected to pin<20> that is the ground pin, which should be connected to ground as instructed above before starting to test anything.

In order to test the 25k resistor connect one end of the multimeter to pin<36> and the other end to pin<37>.
Make sure ground pin<20> is connected to ground.

Connect one end of the multimeter to pin<37> again and the other end to the ground pin<20>.

Connecting pin<20> to ground.
The input signal should be from pin<36>, and to measure the output connect the positive end of the multimeter or the scope to pin<37> and the other end to the ground pin pin<20>.
In the Project report a 5V signal was tested and the output was 1.43V.

Backup

Lab 8 zip file