Lab 6 - EE 421L 

Authored by Your Russ Prado,

prador@unlv.nevada.edu

October 19, 2015

Lab description

Design, Layout, and Simulation of a CMOS NAND gate, XOR gate, and Full-Adder

Part #1:

Tutorial_4 will be needed in completion of this lab. In this tutorial, you will be creating the schematic, symbol, and layout of a 2-Input NAND Gate.

In this lab will also be creating the schematic, symbol, and layout of a 2-Input XOR Gate. With the NAND Gate, XOR Gate, and Inverter Gate(created in Lab 5), we need to run a test to ensure each of these gates are working properly.

2-Input NAND Gate:

The Inverter cell that we created in Lab 5 can be used in making this schematic.

Schematic:

Symbol:

Layout:

Extracted:

DRC & LVS:

2-Input XOR Gate:

Schematic:

Symbol:

Layout:

Extracted:

DRC & LVS:

Gate Test:

 This test is crucial in ensuring that the gates created work properly. He will run pulses on inputs A and B.,

Schematic:

Simulation:

Part #2:

Now that each of the gates are running properly, we can proceed to making the Full-Adder. Like the gates we just created, we must run a simulation to ensure the Full-Adder runs properly.

Full-Adder:

Schematic:

Symbol:

Layout:

This layout if rather lengthy, so a good way to prevent errors is to periodically DRC'ing it.

Extracted:

DRC & LVS:

Simulation:

 Don't forget to back to back your files!

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