Lab 6 - EE 420L
Authored
by Steven Leung
Leungs@unlv.nevada.edu
10/14/2015
Pre-lab work
- Back-up all of your work from the lab and the course.
- Go through Cadence Tutorial 4 seen here.
- Read through the lab in its entirety before starting to work on it
Introduction:
The purpose of this lab is to be able to layout a full adder. A full
adder composes of nand and xor gates. The layout of a full adder will
be done in parts meaning that I will first layout a nand gate and then
an xor gate. Therefore, the full adder can be layed out by calling
these instances of nand and xor gates.
Below is the truth table for a full adder.
a | b | cin | | s | cout |
0 | 0 | 0 | | 0 | 0 |
0 | 0 | 1 | | 1 | 0 |
0 | 1 | 0 | | 1 | 0 |
0 | 1 | 1 | | 0 | 1 |
1 | 0 | 0 | | 1 | 0 |
1 | 0 | 1 | | 0 | 1 |
1 | 1 | 0 | | 0 | 1 |
1 | 1 | 1 | | 1 | 1 |
Below
are a series of pictures that show the layout of an nand gate and
a xor gate along with the DRC and LVS of each.
Note that all mosfets used in the layout of this lab is 6u/.6u
| NAND | XOR |
Schematic | 
Schematic |
Layout | 
Layout |
DRC | 
DRC |
Extracted | 
Extracted
|
LVS | 
LVS |
Below are pictures showing the layout of an inverter.
Schematic | 
Layout |
Extracted |
DRC |
LVS |
|
Simulations of gates
Below
are the schematic and simulation results for the gates that were layed
out above. (each possible input combination is tested)
Note that the symbols in the schematic are generated form the schematic of the corresponding gates shown above.
Schematic |
Simulation results |
Layout of Full Adder
Below are the pictures showing the layout of a Full Adder.
]
Schematic |
Layout |
Extracted |
DRC |
LVS |
Simulation of Full Adder
Schematic |
Simulation Waveform |
From
the waveform shown above, we can see some glitches on the output of
cout and S. This is caused by the rise/fall times of the inputs not
being ideal. During transition times for example when a is falling and
b is falling at the same time, the sum should ideally stay at 1 but
during transition times, there may be a time that the voltage levels
are considered to be low for a brief moment therefore causing the
output to have a false zero. This is a reason why that the matching of
transistors is extremely important becuase if it takes longer for some
MOSFETs to rise/.fall, the length of that false 0 will be significantly
increased.
Design files found here
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