Lab 1 - EE 421L
Authored
by Steven Leung
Leungs@unlv.nevada.edu
Today's date: 8/24
Pre-lab work
- The lab reports will be drafted using html and placed on CMOSedu.
- Prior
to the first day of lab, but no earlier than one week before the lab
starts, get a CMOSedu account, using your UNLV email address, from Dr.
Baker, rjacobbaker@gmail.com
- Review the material seen here covering editing webpages (do this before the first lab)
The main purpose of this lab is to be able to draw my own schematic in Cadence and be able to simulate it.
The first step of this lab is to download Xterm which will be used to remote connect to Candence
There
is quite a bit of setup to be done before being able to simulate your
own files. This includes requesting an account from Dr. Greg and
completeing the following tutorial http://cmosedu.com/cmos1/cadence/remote_x/remote_x.htm
This
first step to creating your own circuit to simulate is to crate a
library for it in the library. I called my library Tutorial_1
The next step is to create a new cell
with a schematic view. This is where the circuit will be
drawn. To look for components use the keybind i (instance) to search
for resistors, voltage sources, ground, etc. To wire the components,
use the bindkey w (wire). Another useful bindkey is f (to fit the
screen).
Before simulating the circuit, launch ADE (Analog Design Environment) and make sure that the simulator is set to spectre.
In the ADC, the subsection analyses is where we can set the type of
simulation or simulation time in this case. Output is where we can set
what nodes we want to take a look at. These are set through the
analyses and output dropdown menus respectively.
To
avoid having to set up the analyses and output everytime we reopen this
circuit, we can save the state through setup -> save state followed
by clicking cellview and ok.
We are now ready to simulate by clicking the green run button. The following should appear.
This is exactly what we expected from the circuit, a 10k 10k voltage divider will yield an output of .5 V when the input is 1 V.
The
background color width of the plot can be changed manually or
automatically by including a few lines in the cdsinit file in the
CMOSedu directory. The specific lines of code can be found at http://cmosedu.com/videos/cadence/cdsinit.htm
This
image shows the lines of code to set spectre to the simulator and the
background to white every time Cadence starts instead of manually doing
it.
Backup
Labs will be zipped and emailed to myself every week as a method of backing up the data.
return to the listing of my labs