Lab 8 - EE 421L Fall 2015

Chip 7

Authored by:

Luis A. Soriano,

sorian20@unlv.nevada.edu

Co Nguyen

nguyec3@unlv.nevada.edu

Mario De La Torre

delatm2@unlv.nevada.edu

11/30/2015 

Zip folder containing Chip7 files found here.

Pre-lab work

• Back-up all of your work from the lab and the course.
• Go through Cadence Tutorial 6 seen here.
• Read through the lab in its entirety before starting to work on it

This tutorial is about placing the circuit from early tutorial into a padframe.
1. Create a pad 75 um.
 

 
2. Once the pad is created we can use it to layout padframe about 1.5mmX1.5mm.
 
Symbol
 

 
Layout
 

 
3.  Now we start with an schematic of all the components in the chip and assign the pins.
 

Form into groups of 4 students that will put the test structures on the chip.
Each test circuit should have its own power but ground should be shared between the circuits.
Power should not be shared between the circuits so that a vdd!-gnd! short in one circuit doesn't make one of the other circuits inoperable.

Your chip should include the following test structures:

• One up/down counter with clear
• The outputs of your counter should be buffered before connecting to a pad
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
• Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)   
• Whatever else you would like to fabricate to use the remaining pins on the chip
• Feel free to "sign" the chip or add a graphic (see the bottom of this webpage). Copy the final, DRC and LVS clean cell you want to fabricate, and then add the graphic since the graphic won't DRC
• Also note that you can reduce the number of pins needed by sharing some of them (two resistors, for example, only need 3 pins)

The following is the final schematic of our chip.
 

Full layout of the MOSIS chip

 Full extract of the MOSIS chip

LVS-no error- of MOSIS Chip

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