Lab 3 - ECE 421L 

Degracia, Manuel C.

degracia@unlv.nevada.edu

14/21 September 2015 

Pre-Lab

Overview

Pre-lab consists of finishing Tutorial #1 from where we left off in Lab #1 (25th image of tutorial).

Continued Process

*Schematic of where we last left off in the tutorial.

7. From the given schematic shown above, we want to create a general purpose schematic which will make it more useful as a cell in an integrated circuit. To do so, delete Vdc and the two wires connected to it and create two pins called in and out. Within the parameters of each pin, make sure each one has the appropriate direction (in = input, out = output). 

Check and Save to verify the schematic has no errors.

8. Create a symbol for this schematic so it can be used in later designs. (Create > Cellview > From Cellview). Follow through with the symbol generation window making sure the pin specifications are correct. Once done, the following generic symbol will be displayed.

9. Delete everything in the symbol except for the in and out pins and wires.

10. Move the pins and lines further apart. Using the draw line command (Create > Shape > Line), draw a generic form of a resistor and ground.

Check and Save the symbol to verify if there are any errors.

11. Simulate the cell's operation to verify it runs properly. Afterwards, create a copy of R_div into another cell called, sim_R_div. Within the sim_R_div cellview, delete spectre_state1 because it is not needed.

12. Open the schematic view of sim_R_div and delete everything in the cell. Next add the R_div symbol using instance (i) and locating the symbol in the Tutorial_1 library found in the component browser. Create the schematic seen below.

Check and Save to verify there are no errors.

13. In this case, 2 errors will be found.

14. Use the following to determine where the issues are located and details about the warnings. (Check > Find Marker)

The floating wires are intentional, thus click Ignore twice and Check and Save again. You'll find that there are no errors or warnings.

15. Simulate the circuit by launching ADE and then load the state. The following transient response should be shown.

16. As a quick side tutorial on hiearchy, by clicking the R_div symbol and pressing X, one can descend into the hiearchy. In addition, pressing b will bring you back up into the hiearchy. If hotkeys are not favorable, one can still follow through the menu options. (Edit > Hierarchy > ...)

Create the layout of the resistive divider

17. Make a new cellview for the layout of R_div.

18. Setup the following items within the Display Properties (e):

• Set the display so that Pin Names are shown.
• Change the Snap Modes to Diagonal.
• Side note: Know how and when to change the Stop Level to see more details in different levels.

• We will use the n-well layer for the 10k resistor.
• The sheet resistance of n-well in the C5 process is roughly 800 ohms.
• The minimum width of the n-well is 12 lambda (3.6 microns since lambda here is 300nm) so lets make a 10k resistor using a width = 4.5um and length = 56um.

 
20. In the n-well layer, draw a generic rectangle (Create > Shape > Rectangle).
 

 
21. Click on the rectangle and press q to edit the parameters (Edit > Basic > Properties). As calculated above, we want a resistor that is 56um long and 4.5um wide.
 

 
22. Design Rule Check the layout (Verify > DRC).
 

 
After running DRC, 4 errors will be found.
 
23. Use Find Marker again to pinpoint the errors and details regarding them.
 

 
24. The issues revolve around the rectangle not being snapped to the y-axis grid. To resolve this issue, we can use a ruler (k) to determine the proper X & Y Snapping measurements and change the values in the Display Parameters (e).
 

 
25. Add connections to the ends of the resistors and add pins to each side in the metal1 layer (Left side = L, Right side = R). To do so, follow the steps shown:
 

 

 
Each corner should be similar to the left ntap displayed.
 
26. Turn the Gravity On control off for easier moving of parts (E) and change the Stop Time to 10 (e) so more layers can be seen.
 
27. Move onto the res_id layer and draw a rectangle in between the two ntaps.
 

  
28. Extract the layout to determine the resistance value (Verify > Extract).
 

 
29. Once extracted, open up the extracted view found in the Library Manager and zoom in to see the resistor value.
 

 
Save and Close the layout view of the resistor.
 
Drawing the layout of the R_div cell
 
30. Open the layout view of the R_div cell and instantiate two 10k n-well resistors. Then, DRC to make sure that they are far enough apart.
 

 
In the metal1 layer, add rectangles to connect the resistors together and to connect to the Pins of the resistors. In addition, add Pins to each corresponding rectangle as displayed above.
 
31. Do the following:

• DRC layout to verify there are no errors or warnings.
• Extract layout
• LVS

32. Once LVS is completed, click Output to see if any problems or errors have occurred.  In this case we have three issues.
 

 
As displayed, there are issues with Pin Names and Pin directions (gnd = gnd!, in = input, out = output).

33. Once fixed, repeat steps #31-32.
 

 
From this, we can finally see that there are no errors or problems and the netlists MATCH! This concludes Tutorial #1.
 
Back-Up Files
As always, it is always important to backup files by either creating a folder on your personal computer, emailing the files to yourself and/or backing it up on a cloud (dropbox, icloud, google drive).

• Use the n-well to layout a 10k resistor as discussed in Tutorial 1 and Pre-lab.
• Discuss how to select the width and length of the resistor by referencing the process information from MOSIS.
• Use the n-well resistor in the layout of your DAC
• Discuss how the width and length of the resistor are measured.
• Parameters:
• Each resistor in the DAC should be laid out in parallel, having the same x-position, but varying y-positions. (Resistors should be stacked)
• All inputs and output pins should be on the metal1 layer.
• DRC and LVS, both the layout and extracted layout.
• Zip up the final design directory and place it in the Lab #3 directory, with a link on the report so the grader can examine both the layout, schematic and simulations.

• The sheet resistance of n-well in the C5 process is roughly 800 ohms.
• The minimum width of the n-well is 12 lambda (3.6 microns since lambda here is 300nm) 
• Given these parameters we can use the following equation to determine the width and length to create a 10k resistor.
• Rtotal = Rsheet (L/W)
• Another parameter to consider is that a given length and width must be divisible by 0.15u in order to "snap to grid".
• To do so, we will use L = 56.1u and W = 4.5u. (Measurements can be verified in the pictures below)

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