EE 421L - Lab 7 - Using Buses and Arrays in the Design of Word Inverters, Muxes, and High-Speed Adders

Jonathan K DeBoy
deboyj@unlv.nevada.edu
19 October 2015
Lab Files

Pre-lab work

 

Introduction

This lab tasked to familiarize ourselves with the array and bus functionality of Cadence. This tool will help us draw more concise schematics and save a lot of times ang effort.

NOT Design




 

NAND Design



 



AND Design



 


NOR Design



 


OR Design



 


Gate Simulations



No connection simulation.


Gate simulation driving 500fF load.





 


MUX Design & Simulations


This multiplexer schematic works via passgates. When select is asserted thigh, the combinations of sel and not sel at the gates of the pmos and nmos of the pass gates will allow a connection from one side to the other. Note that the direction does not matter and this can be used as a demux if a source is placed on the "output".
 



Demux test




   

Full Adder (FA) Design and Layout



Keeping the gates constrained to the poly and metal1 layers made this layout relatively easy since we can hop over everything with metal2.
 

8Bit Full Adder Design and Layout
 


 

 

Simulations



Schematic to test the full adder.

Again, look how the circuit behaves when the inputs change. The logic designer must take these hazards into consideration.
   
Below is a truth table for the full adder which matches up with our waveforms above.
Cin A B S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

 

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