EE 421L - Lab 6 - Design, Layout, and Simulation of a CMOS NAND gate, XOR gate, and Full-Adder

Jonathan K DeBoy
deboyj@unlv.nevada.edu
5 October 2015
Lab Files

Pre-lab work

Back-up all of your work from the lab and the course.
Go through Cadence Tutorial 4 seen here.
Read through the lab in its entirety before starting to work on it

Introduction

This lab tasked to design, layout, and simulate a full adder block that is capable of being cascaded into n number of bits. First off, we have to create the building blocks--NOT, NAND, and XOR gates. After verifying each one individually and making note on their delays and behaviors under operation, we will create a single Full-Adder block that takes in two inputs, a carry-in, and outputs a sum and a carry-out bit.

NOT Design and Layout

NAND Design and Layout

XOR Design and Layout

Full Adder (FA) Design and Layout

Keeping the gates constrained to the poly and metal1 layers made this layout relatively easy since we can hop over everything with metal2.

Simulations

Schematic to test operations of all the gates.	Notice how when both input change at the same time, the xor gate has a static hazard as it pulses to off and then quickly back on.
Schematic to test the full adder.	Again, look how the circuit behaves when the inputs change. The logic designer must take these hazards into consideration.

Below is a truth table for the full adder which matches up with our waveforms above.

Cin	A	B	S	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

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