EE
421L - Lab 5 - Design, Layout, and Simulation of a CMOS Inverter
Pre-lab work
- Back-up all of your
work from the lab and the course.
- Go through Tutorial 3 seen here.
Introduction
This
lab we designed the layout for an Inverter by making use of a single
NMOS and PMOS in a push-pull configuration. We made one 12u by 6u and
the other one 4 times bigger to see the difference in slew.
Inverter Layout
Below are
the schematics, layouts, symbols, and DRC/LVS verifications. Left
column is 1x size and right column is 4x size.
Delay Simulations
Below are the simulation schematics and plots. The left
column is the 1x size and the right column is the 4x. From top down,
each schematic is driving a 100fF, 1pF, 10pF, and 100pF load.
 |
 |
100fF Load |
100fF Load |
1pF Load |
1pF Load |
10pF Load |
10pF Load |
100pF Load |
100pF Load |
Notice how the larger size actually has better slewing? Better as in
it's a much faster since you can output more current since the output resistance
is much smaller compared to the smaller size.
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