EE 421L

EE 421L Digital Integrated Circuit Design - Lab 8

Generating a test chip layout for submission to MOSIS for fabrication

Author: Abel De La Torre
Octover 20th, 2014
delatorr@unlv.nevada.edu

Group 2

Group Memers:

Abel De La Torre
Alan Fortes
Worku Yetneberk

Pre-lab work

Back-up all of your work from the lab and the course.
Go through Cadence Tutorial 6 seen here.
Read through the lab in its entirety before starting to work on it

Your chip should include the following test structures:

30u/0.6u NMOS (3 pins, DN, GN, SN, connect the p+ body, B, of the NMOS to the chip's ground pin)
30u/0.6u PMOS (4 pins, DP, GP, SP, and BP)
Inverter made using 30u/0.6u NMOS and 60u/0.6u PMOS (3 pins, in, out, VDD_inv)
61 stage ring oscillator using 6u/0.6u MOSFETs with off-chip buffer (2 pins, VDD_osc and Ocs_out. Ground connected to pin 20)
20k n-well resistor (2 pins)
20k hi-res poly resistor (2 pins)
1k n+ resistor (2 pins)
1k p+ resistor (3 pins, need n-well to isolate the p+ from the p-substrate and the n-well needs to be tied to a voltage >= either side of the resistor)
Bandgap reference (2 pins, VDD_bg and Vref)
Whatever else you would like to fabricate to use the remaining pins on the chip
Feel free to "sign" the chip or add a graphic (see the bottom of this webpage). Use the nodrc layer around the graphic to ensure that the final chip still passes DRCs.
Also note that you can reduce the number of pins needed by sharing some of them (e.g., you really only need 3 pins for the n-well and hi-res poly resistors). Since only one test structure will be tested at a time this savings can be significant. The savings of pins may be useful if you want to fabricate your lab projects.

The chip is to be tested by inserting it into a bread board and applying the appropriate
stimulus to the component that is desired to be tested. If a resistor is being tested, an
ohm-meter is to be used. Be sure to be aware of the pins designation and purpose,
as we have listed.

Chip Design

                         Pin Selection

    1      30u / 0.6u   Drain
    2      Nmos Ground
    3    Nmos            Source
    4   Pmos    Drain
    5      Same Size    Ground
    6     Pmos            Source
    7     Pmos            Body
    8    Inventer Input
    9     Inverter 30u / 0.6u 60u / 0.6 , Out
    10    Inverter Vdd
    11    Vdd_Osc
    12    61 Stage ring Oscillator, Osc_out
    13 20K Nwell resistor
    14 Nwell resistor
    15    20K High Res Poly
    16    20K High Res Poly
    17 1K P+ Resistor Vdd
    18    Resistor output terminal
    19    resistor Vdd
    20 Ground
    21    1k n+ resistor input terminal
    22    1k n+ resistor output terminal
    23    Bandgap Vdd
    24    Bandgap Output

The following is the final schematic of our chip

         Nmos and Pmos

                30u/0.6u NMOS                              30u/0.6u PMOS

        Inverter
Inverter made using 30u/0.6u NMOS and 60u/0.6u PMOS (3 pins, in, out, VDD_inv)

    The following is the schematic for the Inverter

This is the layout of the Inverter

       61 Ring Oscillator

    The following is the full schematic of the 61 ring oscillator used in the chip design

61 stage ring oscillator using 6u/0.6u MOSFETs with off-chip buffer (2 pins, VDD_osc and Ocs_out. Ground connected to pin 20)
    The following is the layout of the 61 ring oscillator used in the chip design

Resistors P+ and N+

20k n-well resistor (2 pins)
20k hi-res poly resistor (2 pins)
1k n+ resistor (2 pins)
1k p+ resistor (3 pins, need n-well to isolate the p+ from the p-substrate and the n-well needs to be tied to a voltage >= either side of the resistor)

The following is the nwell resistor, 20k ohms.