EE 420L
Analog Integrated Circuit Design Laboratory
Laboratory Report 7: Design of an Audio Amplifier

APRIL 3, 2019

General Overview

This laboratory will regard the design, simulation, and implementation of an audio amplifier with following design requirements.

Design Requirements

· 100 – 20k Hz Frequency Range

· Any number of ZVN3306A and ZVP3306A

· Only one 10 µF capacitor

· Only one 100 µF capacitor

· Assume supply voltage of 10 V

· Audio Signal from MP3 player

· Input resistance of a few kΩ

· 22Ω speaker

· Output resistance around 1Ω

{According to the laboratory sheet, we were asked to use an 8Ω speaker. However, we were given a 22Ω speaker}

Prelab

We reviewed the ZVN3306A and ZVP3306A datasheets. Additionally, we reviewed my laboratory report 6.

Description of Laboratory Procedures: Designing a MOSFET Push-Pull Audio Amplifier

I considered a multi-stage audio amplifier. However, this became challenging as only two capacitors were allowed. Ideally, a coupling capacitor is placed between the stages of multistage amplifiers as seen in Figure 2 (however, this isn’t always the case). These coupling capacitor ensure that each stage has the proper DC biasing. A design requirement given in this laboratory is that only two coupling capacitors may be used (a 10 µF and 100 µF capacitor). Therefore, the easiest way to ensure proper DC biasing is to build an amplifier with a single stage as seen Figure 2.

Figure 1

Figure 2

A push-pull amplifier schematic was given in the laboratory sheet. I decided to use a similar schematic as seen in Figure 3. Without the amplifier, the signal is too weak to drive the 22 Ω speaker. However, with the push-pull amplifier, the signal becomes great enough for the 22 Ω speaker to be driven.

Figure 3

Figure 4

Upon looking at the amplifier schematic given in Figure 3, one can see that the designer may readily alter the performance of the push-pull amplifier by adjusting the resistance values of R1 and R2. Therefore, to gleam what these resistance values should be to better our design – the following SPICE step statements may be made. The result of this simulation is seen in Figure 5.

.step R1 1k 100k 10k

Step R2 from 1kΩ to 100kΩ in increments of 10kΩ.

.step R2 1 100 5

Step R2 from 1Ω to 100Ω in increments of 5Ω.

pushPullDesignParameters

Figure 5

The information presented in Figure 5 can also be presented in Table 1. According to Laboratory Report 6 Equation 184, . The gain is directly proportional to the resistance that connects the gates to the drain. Therefore, it can be said that with a larger gain, one can expect greater output voltage, speaker current, speaker power, MOSFET current, and MOSFET power. Figure 5 and Table 1, may guide a designer to select the proper resistance values of R1 and R2. R2 can determine the output resistance. For instance, an R2 value that matches the load of the speaker will cause the output resistance to half.

Table 1

	R1	R2
Input and Output Voltage	↑	↑
Speaker Current	↑	↑
Speaker Power	↑	↑
PMOS Current	↑	↓
NMOS Current	↑	↓
PMOS Power	Larger Power Swing	↓
NMOS Power	Larger Power Swing	↓

The Power Dissipation Quandary

According to Figure 5 we see that the NMOS power dissipation varies from 0.640-1.2 W and the PMOS power dissipation varies from 1.15-1.7 W depending upon the resistance value configuration. According to the ZVN3306A and ZVP3306A datasheets, we see that the absolute maximum power dissipation rating for both MOSFETS is 0.625 W. Therefore, this amplifier design will result in an amplifier where both MOSFETs exceed the maximum power dissipation rating. This issue could be solved by creating a multi-stage amplifier such that the total gain is achieved by multiple stages. This would result in a decreased average power dissipation in the MOSFETs used. However, this would become troublesome to implement as the design requirements specify that only two capacitors may be used. Therefore, it would be difficult to ensure proper DC biasing for each stage. Therefore, violating the maximum power dissipation rating will cause the NMOSs and PMOSs to overheat eventually destroying them. The circuit as seen in Figure 3 was experimentally built. Due to the maximum power dissipation rating being exceeded; the circuit would eventually destroy itself and render the amplifier nonfunctional.

Table 2

Push-Pull Amplifier Hand Calculations

Figure 6

Under DC analysis, the push-pull amplifier schematic of Figure 3 can be simplified to the schematic as seen in Figure 6. Table 3 demonstrates the properties of the used MOSFETs. While the geometry of each MOSFET is 1.

Table 3

	NMOS		PMOS
	0.1233		0.145
	1.824		2.875

Upon looking at Figure 6, we can say that the drain currents through NMOS and PMOS is identical.

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

Meanwhile, the LTspice simulation gave the following results for the DC biasing as seen in Figure 7.

Figure 7

[9]

[10]

The gain of a push-pull amplifier without a load was determined in Laboratory Report 6 Equations 176-184, resulting in the following:

[11]

The gain may now be calculated as a linear function of R,

[12]

The resistance of R1 plotted against the Gain can be seen in Figure 8 (Plot of Equation 12).

Figure 8

Redesigning the Push-Pull Amplifier and Solving the Power Dissipation Quandary

It became obvious that the push-pull amplifier schematic given in Figure 3 was not adequate due to power dissipation concerns (see The Power Dissipation Quandary section). Therefore, it became necessary to design a power efficient push-pull amplifier. Three approaches were considered:

1. Connecting MOSFETs in Series

2. Adding Diode Connected MOSFETs

3. Adding Resistors

All three approaches were explored via LTspice simulation to ensure feasibility before implementation. To minimize power dissipation amongst MOSFETs in our amplifier design, should be minimized. The important thing to realize is that in all three approaches, the power dissipation of each MOSFET is below the maximum power dissipation rating of 0.625 W.

Approach 1: Connecting MOSFETs in Series

Figure 9

As demonstrated in Figure 9, MOSFETs can be attached in series. When two MOSFETs are attached in series, the lengths of all MOSFETs attached are added together. This concept, is implemented in a push-pull amplifier schematic as seen in Figure 10.

Figure 10

Figure 11

Figure 12

Figure 13

Approach 2: Adding Diode Connected MOSFETs

Another approach would be to add diode connected MOSFETs as demonstrated in Figure 14.

Figure 14

Figure 15

Figure 16

Figure 17

Approach 3: Adding Resistors

The third approach would be to add resistors to the push-pull amplifier in a manner demonstrated in Figure 18.

Figure 18

Figure 19

Figure 20

Figure 21

Summarizing the Three Approaches

The first and third approach compete neck to neck in the LTspice simulations. However, the third approach would be cheaper and easier to implement with discrete components. The second approach provides insufficient current and power to drive the speaker. Therefore, the third approach will be implemented.

Final Design

The final implemented design on the breadboard was the schematic as seen in Figure 18. In Figure 22, one can see the frequency response of the final design. Figures 22-25 demonstrates the behaviour of the final design. Table 4 summarizes the the behaviour of the final design.

Figure 22: Frequency Response in LTspice (LOG)

Figure 23: Frequency Response in LTspice (LINEAR)

Figure 24: Net Power Consumption

Figure 25: Input Resistance

Figure 26: Output Resistance

Table 4

Parameter	Value
Gain (With Load)	-0.739.33 V/V
Net Power Consumption	0.84 W
Rin	63.24kΩ
Rout	11Ω

Experimental Results

The final design was implemented on the breadboard as seen in Figure 26. A YouTube video demonstrating the function of the amplifier can be viewed by clicking on Figure 27. The required frequency range is proven by Figure 28. The final design could operate indefinitely; without the transistors burning up.

Figure 27

Figure 28

Figure 29

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