EE 420L
Analog
Integrated Circuit Design Laboratory
Laboratory
Report 6: Single-Stage Transistor Amplifier
AUTHOR:
Bryan Kerstetter
EMAIL:
kerstett@unlv.nevada.edu
March
27, 2019
General
Overview
This laboratory introduces students to physical
MOSFETs. The MOSFETs used in this laboratory in ZVN3306A and
the ZVP3306A.
Prelab
I watched Dr. Baker’s video about single-stage
MOSFET amplifiers while also reviewing the concepts covered in my Laboratory
Report 5.
Description
of Laboratory Procedures
{The
NMOS and PMOS parameters can be
easily ascertained in a LTspice model by accessing
the error log (push CONTROL L)}
Source
Follower (Common-Drain Amplifier)
The source follower or the common-drain amplifier of
the NMOS and PMOS types can be seen in Figure 1. The circuit as seen in Figure
1 was implemented on the breadboard.
NMOS
Hand Calculations
DC
ANALYSIS
ZVN3306A Parameters
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
For the NMOS to be on 
,
[12]
[13]
AC
ANALYSIS
[14]
[15]
[16]
[17]
[18]
Substituting, Eq. 16 and Eq. 17 into Eq. 18 gives us,
[19]
INPUT
AND OUTPUT RESISTANCE
[20]
[21]
PMOS
Hand Calculations
DC
ANALYSIS
ZVP3306A Parameters
[22]
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
[31]
[32]
For the PMOS to be on 
,
[33]
[34]
AC
ANALYSIS
[35]
[36]
[37]
[38]
Substituting, Eq. 37 into Eq. 38,
[39]
Additionally,
[40]
Substituting, Eq. 39 into Eq. 40,
[41]
Solving for gain,
[42]
[43]
INPUT
AND OUTPUT RESISTANCE
[44]
[45]
Simulation,
Theory, and Operation
In
general, the gain of the source follower is determined by the resistance
connected to the source of the MOSFET. Equation 46 explains how the gain of the
source follower is determined.
[46]
Therefore,
in this situation the gain of the NMOS source follower is determined by R2 and
the gain of the PMOS source follower is determined by R6. In some scenarios, the
source follower can be used as a voltage buffer. A voltage buffer protects the
input signal from whatever current the load draws. Here, in Figure 2 and 3, we
may see that the LTspice simulation confirms the hand
calculations demonstrated previously. Experimentally, we had to choose a
frequency such that the capacitor impedance was negligible but not so high that
the gain is dropping off. Additionally, we used an electrolytic capacitor for
C1 and C2. We made sure that the positive terminal of the capacitor was
connected to the gate of the MOSFET.
Figure 1
Figure 2
Figure 3
Concerning
all Portions of the Laboratory: Measuring Input and Output Resistance
Input
Resistance
To measure the input resistance of an amplifier, one
may place a resistor of the theoretical calculated input resistance in between
the input voltage source and the amplifier. To experimentally calculate the
input resistance, one has to determine the peak AC current and voltage. The
peak AC current may be determined by measuring the voltage drop over this
resistor. The experimental peak AC current may be determined by Equation 47.
[47]
The peak AC input voltage can be determined by measuring the
signal left of the coupling capacitor. Finally, the input resistance can be
calculated by Equation 48.
[48]
Output
Resistance
To measure the output resistance, a resistor equal to
the theoretical calculated output resistance in series with a big capacitor.
This capacitor is connected to the output voltage and the resistor. The
capacitor’s purpose is to avoid the messing up the DC operating point of the
amplifier. The peak AC gate-source voltage and output current must be
determined to experimentally determine the amplifier’s output resistance.
[49]
[50]
[51]
NMOS
Source Follower Experimental Results
Figure 4: NMOS Source Follower, VinN and VoutN
Figure 5: NMOS Source Follower, Voltage drop over Rin = 33.33k Ohms
[52]
[53]
[54]
[55]
[56]
Figure 6: NMOS Source Follower, Voltage drop over Rout = 52 Ohms
Figure 7: NMOS Source Follower, Rout, AC VGS
[57]
[58]
[59]
[60]
[61]
PMOS
Source Follower Experimental Results
Figure 8: PMOS Source Follower, VinP and VoutP
Figure 9: PMOS Source Follower, Voltage Drop over Rin = 33.33k Ohms
Figure 10: PMOS Source Follower, Peak Input Voltage
[62]
[63]
[64]
[65]
[66]
Figure 11: PMOS Source Follower, Voltage drop over Rout = 82 Ohms
Figure 12: PMOS Source Follower, Rout, AC VGS
[67]
[68]
[69]
[70]
[71]
Common-Source
Amplifier
Simulation,
Theory, and Operation
The gain of the common-source amplifier can be determined in the
following manner according Equation 72.
[72]
A
PMOS and NMOS common-source amplifier can be seen in Figure 13. The circuit as
seen in Figure 13 was implemented on the breadboard and experimentally tested.
Figure 13
Figure 14
Figure 15
Common-Source
Amplifier Hand Calculations
NMOS
Hand Calculations
{Assume
identical DC biasing}
AC
ANALYSIS
ZVN3306A Parameters
[73]
[74]
[75]
[76]
We may calculate the small signal gain,
[77]
[78]
Therefore,
[79]
[80]
Substituting, Eq. 79 into Eq. 80,
[81]
[82]
Therefore, we may define the AC drain current in two ways,
[83]
[84]
Substituting, the first definition of 
in Eq. 83 into Eq. 84,
[85]
[86]
INPUT
AND OUTPUT RESISTANCE
[87]
[88]
PMOS
Hand Calculations
AC
ANALYSIS
ZVP3306A Parameters
[89]
[90]
[91]
[92]
The parallel resistance connected at the source can be
simplified to a single resistor.
[93]
We may calculate the small signal gain,
[94]
[95]
[96]
[97]
[98]
[99]
[100]
[101]
[102]
[103]
INPUT
AND OUTPUT RESISTANCE
[104]
[105]
NMOS
Common-Source Experimental Results
Figure 16: NMOS Common-Source, VinN and VoutN
Figure 17: NMOS Common-Source, Voltage Drop over Rin = 33.33k Ohms
[106]
[107]
[108]
[109]
[110]
Figure 18: NMOS Common-Source, Voltage Drop over Rout = 1k Ohms
Figure 19: NMOS Common-Source, Rout VGS
[111]
[112]
[113]
[114]
[115]
PMOS
Common-Source Experimental Results
Figure 20: PMOS Common-Source, VinP and VoutP
Figure 21: PMOS Common-Source, Voltage Drop over Rin = 33.33k Ohms
[116]
[117]
[118]
[119]
[120]
Figure 22: PMOS Common-Source, Rout VGS
Figure 23: PMOS Common-Source, Voltage
Drop over Rout 1k Ohms
[121]
[122]
[123]
[124]
[125]
Source
Resistance and Gain
As demonstrated by Equation 72, which states,
[72]
The total resistance in the source is inversely proportional to
the gain of the common-source amplifier as demonstrated by Equation 126.
[126]
Therefore, when there is greater resistance in the source, there
will be smaller gain. Likewise, when there is smaller resistance in the source,
there will be greater gain. A LTspice model was used
to verify this fact. Figure 24, demonstrates that a low source resistance leads
to greater signal gain. Figure 25, demonstrates that high source resistance
leads to smaller signal gain.
Figure 24: RSN and RSP = 10
Figure 25: RSN and RSP = 1000
Common-Gate
Amplifier
Simulation,
Theory, and Operation
The common-gate amplifier is another MOSFET amplifier topology.
The gain of the common-gate amplifier can be described in Equation 127.
[127]
Therefore, for the NMOS Common-Gate amplifier, the gain is
dependent upon R8, R2, and RSN. Additionally, for the PMOS Common-gate
amplifier, the gain is dependent R6, R7, and RSP. Figure 26 depicts the LTspice model used to simulate the circuit. Figure 27 shows
the transient simulation. While, Figure 28 shows the frequency response. Therefore,
it can be seen that the small signal gain is inversely portioned to RSN and
RSP.
Figure 26: PMOS and NMOS Common-Gate Amplifiers
Figure 27: Input and Outputs
Figure 28: Frequency Response
Common-Gate
Amplifier Hand Calculations
NMOS
Hand Calculations
{Assume
identical DC biasing}
AC
ANALYSIS
ZVN3306A Parameters
[128]
[129]
[130]
[131]
We may now calculate the small signal voltage gain,
[132]
[133]
[134]
Substituting Eq. 134 into Eq. 133,
[135]
[136]
Substituting, Eq. 136 into Eq. 132,
[137]
[138]
INPUT
AND OUTPUT RESISTANCE
[139]
[140]
PMOS
Hand Calculations
ZVP3306A Parameters
[141]
[142]
[143]
[144]
Now we may calculate the small signal gain,
[145]
[146]
[147]
[148]
[149]
[150]
[151]
[152]
INPUT
AND OUTPUT RESISTANCE
[153]
[154]
NMOS
Common-Source Experimental Results
Figure 29: NMOS Common-Gate, VinN and VoutN
Figure 30: NMOS Common-Gate, Voltage Drop over Rin = 150 Ohms
[155]
[156]
[157]
[158]
[159]
Figure 31: NMOS Common-Gate, Voltage Drop over Rout = 1k
Figure 32:NMOS Common-Gate, Rout VGS
[160]
[161]
[162]
[163]
[164]
PMOS
Common-Source Experimental Results
Figure 33: PMOS Common-Gate, VinP and VoutP
Figure 34: PMOS Common-Gate, Voltage Drop over Rin = 182 Ohms
[165]
[166]
[167]
[168]
[169]
Figure 35: PMOS Common-Gate, Voltage Drop over Rout = 1k Ohms
Figure 36: PMOS Common-Gate, Rout VGS
[170]
[171]
[172]
[173]
[174]
Push-Pull
Amplifier
Simulation,
Theory, and Operation
The push-pull amplifier consists of two MOSFETS. The
two MOSFETs are connected at the drain. The configuration can be likened to an
inverter. The push-pull MOSFET amplifier topology allows for a device that
allows the output to swing from rail to rail (VDD to GND). This wide voltage
swing is one benefit of the push-pull amplifier. Positive AC current causes the gates of both
MOSFETs to rise in voltage. Such that the positive current leads to the PMOS
being turned off. While, the NMOS is on. The situation of negative AC current
leads to a state where PMOS is on and the NMOS is off. The amplifier is either pushing or pulling current to or from the output. Therefore, the amplifier
topology will be expected to source and sink current well. The input source can
either be placed on either the NMOS or PMOS gate. Based upon, the LTspice simulation as seen in Figures 37 and 38, one can
see that the push-pull amplifier has great gain. One can easily adjust the gain
of the amplifier by adjusting the resistance of R1.
[175]
Figure 37: Push-Pull Amplifier, R1 = 100k Ohms, Vin = 1mV AC
Figure 38: Push-Pull Amplifier, R1 = 100k Ohms, Vin = 1mV AC
Figure 39: Push-Pull Amplifier, R1 = 100k Ohms, Vin = 1mV AC
To prove Equation 175, we may conduct an additional LTspice simulation. In Figure 40, we see that a larger
resistance leads to greater gain. In Figure 41, we see that a smaller
resistance leads to less gain.
Figure 40: Push-Pull Amplifier, R1 = 500k Ohms, Vin = 1mV AC
Figure 41: Push-Pull Amplifier, R1 = 1k Ohms, Vin = 1mV AC
In the laboratory, we incorrectly used a large input
signal for our push-pull amplifier. This caused our output to rail. We should
have used a smaller input signal. The following demonstrates, that a large
input signal leads the amplifier’s output to swing rail to rail. The
experimental results, show that a push-pull amplifier allows for the output to
swing from rail to rail. Figure 42 depicts a LTspice
simulation where the push-pull amplifier parameters lead to an output signal
that clipped. This clipping could have been eliminated by using a smaller input
signal or feeding the input signal through a voltage divider.
Figure 42: Push-Pull Amplifier, R1 = 100k Ohms, Vin = 20mV AC
Common-Gate
Amplifier Hand Calculations
AC
ANALYSIS
Determine the small signal voltage gain of the
push-pull amplifier:
Regarding the PMOS,
[176]
[177]
Regarding the NMOS,
[178]
[179]
Performing nodal analysis,
[180]
Substituting Eq. 177 and Eq. 179 into Eq. 180,
[181]
We can define the AC output voltage to be,
[182]
Substituting Eq. 181 into Eq. 182,
[183]
Giving us the general formula that describes the small signal
voltage gain for this specific push-pull MOSFET amplifier topology,
[184]
Note that in both situations, the DC biasing is the same.
When R = 100k:
Figure 43: LTspice
[184]
[185]
When R = 510k:
Figure 44: LTspice Error Log
[186]
[187]
Experimental
Results
Figure 45: Push-Pull Amplifier with 100k Ohm Resistor
Figure 46: Push-Pull Amplifier with 500k Ohm Resistor
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