EE 420L
Analog
Integrated Circuit Design Laboratory
Laboratory
Report 3: Op-Amps I, Basic Topologies, Finite Gain, and Offset
AUTHOR:
Bryan Kerstetter
EMAIL:
kerstett@unlv.nevada.edu
FEBRUARY 14, 2019
General
Overview
This laboratory regards the review of basic
Operational Amplifier topologies; while, introducing non-ideal op amps, finite
gain, and offset.
Prelab
I watched Dr. Baker’s video
about op amps while reviewing concepts covered on my Laboratory
Report 2.
Description
of Laboratory Procedures
{During
this laboratory we assume that VCC+ =
+5V and VCC- = 0V.}
{For
oscilloscope images, assume that the
yellow and blue traces are the input and output signals, respectively}
The LM324 Operational Amplifier
This laboratory extensively uses the LM324 Low Power
Quad Operational Amplifier Integrated Circuit. The range of common mode
voltage (VCM) is from 0 V to 
,
such that 
is not greater than 30V (see Figure 1). A good estimate for the op-amp’s open-loop gain
can be seen in Figure 2. For instance, at a frequency of 100 Hz the open loop
voltage gain is 80 dB. The LM324 offset voltage is
typically 2 mV (see Figure 3). Generally, a designer should consider that
maximum value, that way the design can accommodate the extremes. Therefore, I
would consider the worst case offset voltage of 9 mV, while executing a design.
Figure 1
Figure 2
Figure 3
Circuit One
Figure 4
|
|
Theoretical
Value |
Experimental
value |
|
RF |
5 kΩ |
5.0638 kΩ |
|
RI |
5 kΩ |
5.0638 kΩ |
|
R1 |
10 kΩ |
9.9716 kΩ |
|
R2 |
10 kΩ |
9.9716 kΩ |
|
C1 |
0.01 uF |
9.322 nF |
|
C2 |
0.01 uF |
9.322 nF |
Figure 5
Circuit
One Overview, Decoupling Capacitors, and the Voltage Divider
Figure 4 depicts Circuit One. Here we see an inverting
op amp topology with a gain of -1 (Equation 3). VCC+ is connected to 5 V. VCC-
is connected to ground. The common mode voltage is produced by a voltage
divider. C1 and C2 are decupling capacitors.
Decoupling capacitors are used to even voltage out in the event of
slight variance in the voltage from the power supply. Decoupling capacitors do
not need to have specific capacitance values. Therefore, capacitance values
such as 0.1 µF, 1000 pF, and 1 µF could all be used. When a larger decoupling
capacitor is used; the startup time is longer. However, when a smaller
decoupling capacitor is used; the startup time is shorter. If the resistances
R1 and R2 are much larger (assuming that they both are equal in resistance);
there will be little change. If R1 and R2 remain equal, the voltage divider will
split the voltage in half. However, there will be issues regarding the bias
current if the resistances of R1 and R2 are too great (this will be discussed
later).
Common
Mode Voltage
The common mode voltage or VCM can be considered as
the reference voltage on which op amp output signals ride. Generally, VCM can
be found by taking the mean of VCC+ and VCC- Equation 1.
[1]
Our VCC+ is 5V and our VCC- is 0V. Therefore, our
common mode voltage or VCM is 2.5 volts. VCM is achieved by the voltage divider
described above. VCM will remain constant assuming that the supply voltage,
VCC, remains constant.
Ideal
Closed Loop Gain
The ideal closed loop gain for an inverting op amp
topology can be described by Equation 2.
[2]
[3]
Equation 3 shows that there will be no amplitude gain in our op
amp circuit. However, the op amp circuit will invert the input signal.
Therefore, the input and output signals will have a 180º phase difference.
LTspice Simulation with Experimental Parameters
A LTspice model (Figure 6) was created
such that all experimental values listed in Figure 5 are implemented. A netlist
of the LM324 IC provided by National Semiconductor was used to effectively
model the LM324 IC in LTspice. In Figure 7, the open
loop gain was confirmed.
Figure 6
Figure 7
Experimental
Results
We implemented the circuit described in Figure 4 on the bread board
as seen in Figure 8. Figure 9 shows the experimental results while inspecting
both the input and output signals. The output signal has some distortion its
trough. Interestingly, when we replaced RF and RI with larger resistance
values, this trough distortion in the output signal was removed. This will be
demonstrated later. The output swing of the input and output signals are both
100 mV. Figure 10 shows the input and out signals under DC coupling. Figure 10
shows that both signals are riding on top of 2.5V. This is due to the fact that
both the DC Shift of the signal and VCM are at 2.5 V.
Figure 8
Figure 9
Figure 10
One might ask, what happens when the input signal is
not centered around VCM. We selected an input signal DC offset of 4 V (Figure
11) and 2V (Figure 12). The DC offset had to be within a certain range. If the
DC offset was outside this range, then clipping of the output signal would
occur. For an input signal DC offset of 4 V, the output signal was riding 1
V. While, for an input signal DC offset
of 2 V, the output signal was riding 3 V. Adding a DC offset to the input
signal adds to the net offset of the op amp.
Figure 11
Figure 12
Op
Amp Input Bias and Input Offset Currents
Figure 13
According to the LM324 datasheet, the op amp has an
input bias current that flows in or out of the op amp’s input terminals. The
flow of the input bias currents can be seen in Figure 13. This bias current is
usually flows out of the op amp’s input terminals at around 20 nA. This current flows though the electrical devices
connected to the input terminals. While considering the input bias current of
an op amp, one might wonder how this current would effect R1 and R2. If R1 and
R2 are larger the voltage drops over these resistances due to the input bias
current will be larger. If these voltage drops (over R1 and R2) are too large,
VCM and VM will differ. Likewise, by increasing, RF and RI, the voltage drops
across these resistors become larger, due to Ohm’s Law. Also resulting in VCM
and VM to differ. Thereby, adding to the net offset voltage. Offset voltage,
due to bias currents, result in input offset current. Input offset current is
the difference of the input bias
current (Input Offset Current = Non-Inverting
Bias Current – Inverting Bias Current).
Figure 14
Figure 15
Figure 16
Figure 17
Experimentally, we placed 10 MΩ resistors for RF
and RI. We replaced RF and RI with the 10 MΩ to minimize trough
distortion in our output signal. The input bias and offset currents can effect
this decision to replace RF and RI. Figure 14 and 15 show the experimental
results where RF and RI are 10 MΩ resistors. Comparing Figure 14 & 15
(RF = RI = 10 MΩ) with Figure 11 & 12 (RF = RI = 5 kΩ),
little difference is seen. The most noticeable difference can be seen in trough
of the output signal. When RF = RI = 5 kΩ, distortion in the trough is
apparent. However, when RF = RI = 10 MΩ, this distortion is removed. From
this point on, all experimental iterations of Circuit One exist such that RF =
RI = 10 MΩ. Figure 16 and 17 show the experimental results where R1 and
R2 are 10 MΩ resistors.
Maximum
Allowable Input Signal Amplitude
The maximum allowable input signal should have an
amplitude less than 2.5V due to the values of VCM, VCC+, and VCC-. We
experimentally measured the maximum allowable input signal by slowly dialing up
the input signal amplitude on the function generator. We raised the amplitude
until we saw clipping of the output signal. When the input signal was 3.070 Vpp (Figure 18); we began to see clipping of the output
signal (Figure 19). Therefore, the
maximum experimental input signal amplitude is 1.535 V.
Figure 18
Figure 19
To confirm our experimental results, the LTspice model (with experimental parameters) given in
Figure 6 was re-simulated with an input signal amplitude of 1.535 V (Figure 20
& 21). Comparing the waveforms in Figure 19 and Figure 21, we see that they
are both in agreement. Therefore, our experimental results are confirmed. Note,
the clipping on the peak of the output signal on both the experimental and LTspice waveforms.
Figure 20
Figure 21
Gain
of -10: Maximum Allowable Input Signal Amplitude
Now let’s say that we adjust the resistances of RF and
RI such that the inverting op amp topology has a gain of -10. According to
Equation 2, let RF = 10 kΩ and RI = 1 kΩ. Previously, we determined
that for a gain of -1, the maximum input signal gain is 1.535 V. By increasing
the gain to -10V, we may determine the maximum allowable input signal amplitude
based upon our previous results.
[4]
Equation 4 is confirmed by the LTspice
simulation given in Figure 22 & 23. Note, the clipping on the peak of the
output signal as seen in Figure 23.
Figure 22
Figure 23
Circuit Two
Figure 24
Measuring
the Offset Voltage of the LM324 Op Amp
Circuit Two as depicted in Figure 24 can be used to
measure an op amp’s offset voltage. You may measure the offset voltage with
this circuit due to the fact that RF > RI. The offset voltage can be
determined by measuring the difference in voltage between the output voltage
and the VCM voltage. Initially, we tried to measure the offset voltage with RF
being equal to 20 kΩ. There was little difference between the two voltages.
This little difference was very difficult to measure. The laboratory
instructions indicated this difference can be increased by replacing RF with a
resistor that is 100 kΩ or larger. We tried letting RF = 100 kΩ
(Figure 25). The voltage difference was still small. So, we decided to use a 1
MΩ resistor (for RF) so that our measurements would be more precise
(Figure 26). This increased our gain to 1000 and allowed us to easily measure
the voltage difference.
Figure 25: LM324 (RF = 100 kΩ)
Figure 26: LM324 (RF = 1 MΩ)
In this case (Figure 26), we see that the voltage
difference is 
Therefore, the offset voltage can be found by
Equation 5.
[5]
Accord to the LM324 data sheet, we see that a typical offset
voltage typically around 2 mV. We measured the offset voltage to be 0.64 mV.
Measuring
the Offset Voltage of Three Additional Op Amps: The UA741, LM741, and the
LM348N
We applied the procedure as described above to measure the
offset voltage of three additional op amps.
Figure 27: UA741 ( RF = 1 MΩ)
[6]
Figure 28: LM741 (RF = 1 MΩ)
[7]
Figure 29: LM348N (RF = 1 MΩ)
[8]
We can the compare the measured offset voltages of four op amps
as seen in Figure 30.
|
|
Measured
Offset Voltage |
|
LM324 |
0.64 mV |
|
UA741 |
0.26 mV |
|
LM741 |
1.84 mV |
|
LM348N |
1.04 mV |
Figure 30
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