EE 420L
Analog
Integrated Circuit Design Laboratory
Laboratory
Report 1: Review of Basic RC Circuits
AUTHOR:
Bryan Kerstetter
EMAIL:
kerstett@unlv.nevada.edu
JANUARY
30, 2019
General
Overview
This laboratory regards the introduction of editing
webpages in HTML on CMOSedu. While, also reviewing
basic RC circuits both theoretically, experimentally, and by LTspice
simulation.
Prelab
A CMOSedu account was
requested for this laboratory and an index page was created.
Figure 1 [Index webpage as viewed on 1/29/2019]
Description
of Laboratory Procedures
This laboratory regards three circuits given in Dr. Baker’s book (CMOS: Circuit
Design, Layout, and Simulation – Third Edition). The three circuits are the
circuits seen in Figs. 1.21, 1.22, and 1.24 (while replacing the 1pF capacitor
with a 1µF capacitor).
Circuit One
Figure 2 [Fig. 1.21 in CMOS book]
Hand
Calculations to Detail Circuit’s Operation
This circuit is a voltage divider.
[1]
Giving us the following transfer function:
[2]
The magnitude response can be defined such that:
[3]
[4]
The phase response can be determined such that:
[6]
[7]
Therefore, it can be said that output signal lags (as
denoted by the negative parity of 
) behind
the input signal by 715.3 µs.
LTspice
Simulation
Figure 3
Figure 4
According to LTspice the output signal lags behind the input
signal by ~723.3 µs.
Figure 5
Therefore, this circuit is a simple low-pass filter.
Vin remains unchanged across frequency due to the fact that the input voltage
source does not have a specified series resistance.
Experimental
Results
Due to component availability, the following values
were used:
·
R = 1.1977 Ω
·
C = 0.9972 µF
Figure 6
|
|
Vpp |
Amplitude |
|
Input
Signal |
2.06 Vpp |
1.06 V |
|
Output
Signal |
1.20 Vpp |
610mV |
Figure 7
Experimental
Frequency Response
A video was created where a frequency sweep was
implemented such that one can easily see the circuit’s frequency response. This
video can be viewed here. The
frequency range seen in the video is 4 Hz – 2 kHz.
|
Frequency |
Input Voltage |
Output Voltage |
Phase |
|
10 Hz |
2.2 Vpp |
2.08 Vpp |
7ş |
|
100 Hz |
2.2 Vpp |
1.64 Vpp |
37ş |
|
1k |
2.12 Vpp |
0.34 Vpp |
60ş |
|
10 kHz |
2.08 Vpp |
0.043 Vpp |
-16ş |
|
100 kHz |
2 Vpp |
0.0176 Vpp |
-160ş |
|
1 MHz |
2 Vpp |
0.014 Vpp |
-160ş |
Figure 8
The decrease in the input voltage is due to the series
resistance of the function generator (see Circuit Two section below for further
explanation).
Figure 9
Comparing
Hand Calculations, LTspice Simulation, and Experimental Results
|
|
Hand
Calculations |
LTspice Simulation |
Experimental Results |
|
Amplitude |
623 mV |
622.59 mV |
610mV |
|
Phase |
-51.5 |
-52.07 |
-58.38 |
|
Time
Difference |
-715.3 µs |
-723.3 µs |
-810.833 µs |
Figure 10
Variances in respective values found by hand
calculations, LTspice, and experimental results are partl
due to the fact that the resistance and capacitance values were not ideal.
Circuit Two
Figure 11 [Fig. 1.22 in CMOS book]
Circuit Two is really similar to Circuit One. However,
Circuit Two has a 2µF bypass capacitor in parallel with the 1k resistor. Interestingly, this circuit is the circuit
for a compensated scope probe without the load of the oscilloscope.
Figure 12 [Fig. 10.24 in CMOS book]
Hand
Calculations to Detail Circuit’s Operation
Similar to Circuit One, Circuit Two can be simplified
down to a voltage divider.
[8]
[9]
The following transfer function can be developed to represent
the system:
[10]
The magnitude response can be calculated such that:
[11]
[12]
The phase response can be determined such that:
[13]
[14]
Therefore, it can be said that output signal lags (as
denoted by the negative parity of ) behind
the input signal by 95 µs.
Interestingly, at high frequencies Vout
converges at the following (working off of eq. 9):
[15]
Eq. 15 leads to the fact that Vout
would never converge at zero (without factoring function generator series
resistance). However, this approach does not account for the series resistance
of the function generator. Thereby, changing our circuit to the one seen in
Figure 13. Where R2 is the series resistance of the function generator. This
alternative circuit would have to be used to effectively model Circuit Two
physically constructed. Circuit analysis would then be used to predict the
behavior of Circuit Two, physically constructed.
Figure 13: Modified Circuit Two
LTspice
Simulation I
Note, that for this LTspice no series resistance was
implemented. This is due to the fact that Fig. 1.22 in the CMOS book specified
no series resistance. Therefore, this particular
LTspice simulation will not accurately predict the frequency response of this
circuit in real life (most notably, that of the input signal).
Figure 14
Figure 15
According to LTspice the output signal lags behind the input
signal by ~115 µs.
Figure 16
It should be noted that this bode plot indicates that
the input signal remains unchanged throughout all frequencies. This will not
hold to be true in the experimental results.
Experimental
Results
Due to component availability, the following values
were used:
·
R = 1.1977 Ω
·
C1 = 2.088 µF
·
C2 = 0.9972 µF
Figure 17
|
|
Vpp |
Amplitude |
|
Input
Signal |
2.10 Vpp |
1.08 V |
|
Output
Signal |
1.52 Vpp |
770mV |
Figure 18
Experimental
Frequency Response
A video was created where a frequency sweep was
implemented such that one can easily see the circuit’s frequency response. This
video can be viewed here. The
frequency range seen in the video is 20 Hz – 7 kHz.
|
Frequency |
Input Voltage |
Output Voltage |
Phase |
|
10 Hz |
2.2Vpp |
2.06Vpp |
13 |
|
100 Hz |
2.2Vpp |
1.56Vpp |
10 |
|
1k |
2.08Vpp |
1.36Vpp |
2 |
|
10 kHz |
1Vpp |
0.64Vpp |
-10 |
|
100 kHz |
0.248Vpp |
0.144Vpp |
-76.725 |
|
1 MHz |
0.232Vpp |
0.12Vpp |
Unable to
measure |
Figure 19
Figure 20
Note the drastic decay in the input voltage.
Figure 21
LTspice
Simulation II
Unfortunately, the hand calculations and LTspice
simulation failed to predict the decay of the input signal at greater and greater
signals. Recall, that there was also decay of the input signal in Circuit One.
However, this decay was far less due to the fact that Circuit One did not have
a bypass capacitor in parallel with its resistor.
A new LTspice model can be created based upon the
circuit described in Figure 13. This new LTspice model will accommodate the
series resistance of function generator. The series resistance was
experimentally measured by an ohmmeter. The results of these measurements can
be seen in the table below.
|
Output
Frequency |
Series
Resistance of Function
Generator |
|
30 kHz |
12 Ω |
|
100 kHz |
40 Ω |
|
1 MHz |
65 Ω |
Figure 22
Our new LTspice model will include an input voltage
source with a series resistance of 65.
Figure 23
Figure 24
Here, our LTspice model shows the decay of the input
signal voltage. This decay of the input signal voltage was observed
experimentally. However, even this new LTspice model is not entirely
representative of physical circuit. The series resistance of the input signal
voltage would have to vary with frequency.
Comparing
Hand Calculations, LTspice, and Experimental Results
|
|
Hand
Calculations |
LTspice
Simulation
I |
Experimental Results |
|
Amplitude |
694 mV |
694.923 mV |
770 mV |
|
Phase |
-6.84 |
-8.28 |
-8.5 |
|
Time
Difference |
-95 µs |
-115 µs |
-118.056 µs |
Figure 25
Variances in respective values found by hand calculations,
LTspice, and experimental results are partly due to the fact that the
resistance and capacitance values were not ideal.
Circuit Three
Circuit Three is very identical to Circuit One. The
only difference is the input signal of the circuit. In Circuit One, the input
signal is a sinusoidal wave. Whereas, in circuit three, the input signal is a
square wave.
Figure 26 [Fig. 1.24 in CMOS book -- modified]
Hand
Calculations to Detail Circuit’s Operation
The input signal given in Fig. 1.23 of the CMOS book
could not be used because the capacitance of C1 was changed from 1pF to 1µF.
Changing the capacitance of C1; also, changes the value of the RC time
constant.
[16]
[17]
[18]
[19]
After
the system will reach a steady-state (Equation
17). Therefore, to effectively observe the charging and discharging of the
capacitor, we may let the capacitor charge and discharge for 5 ms, respectively
(50% duty cycle). This gives an input signal with a period of 10 ms and giving
us a frequency of 100 Hz. Additionally, it can be said that take 700 
to charge or discharge 50% of its steady state
value (Equation 18). The rise and fall times are defined to be 2.2 ms (Equation
19). The trace of the capacitor charging
or discharging can be described by:
[20]
|
|
Positive Edge of |
|
|
Negative Edge of |
|
|
Start Time |
Figure 27
Equation 20 gives us the following piecewise function to
describe Vout over one period under the specified
input signal.
[21]
All of the above hand calculations can be graphically depicted
as seen in Figure 28.
Figure 28 [Graphed by the online Desmos
Graphing Calculator and annotated in PowerPoint]
LTspice
Simulation
In LTspice, the square wave described in Figure 26 can
be achieved by the following pulse statement:
PULSE(0 1 0 10n 10n 5m 10m)
Figure 29
Figure 30
Experimental
Results
Due to component availability, the following values
were used:
·
R = 1.1977 Ω
·
C = 0.9972 µF
Figure 31
Comparing
Hand Calculations, LTspice Simulation, and Experimental Results
The hand calculated, LTspice,
and experimental waveforms are in agreement as seen in Figure 32.
|
|
Hand
Calculations |
LTspice
Simulation |
Experimental
Results |
|
|
700 |
~697.67 |
816.0 |
|
|
2.2 ms |
~2.3 ms |
2.420 ms |
|
|
2.2 ms |
~2.3 ms |
2.367 ms |
Figure 32
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420L Spring 2019 Page
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