ECE 5/418 Memory Circuit Design
Spring 2011, Boise State University

 

The CMOSedu.com Google groupís (http://groups.google.com/group/cmosedu) and the email address is CMOSedu@googlegroups.com

 

Lecture notes are here

Current grades are here

 

Instructor: Jake Baker
Time: Mondays and Wednesdays, 7:30 to 8:45 PM

Course dates: Wednesday, January 19 to Wednesday, May 4

Location: MEC 206

Holidays: February 21 (Presidentsí day), March 28 and 30 (Spring break from instruction)
Final Exam time: Wednesday, May 11, 6 to 8 PM

Course Description: Transistor level design of memory circuits. Memory technologies including DRAM, Flash, MRAM, Glass-based, and SRAM will be discussed. A practical introduction to the design of memory circuits. PREREQ: ECE 5/410 Integrated Circuit Physical Design.

Textbooks:  CMOS Circuit Design, Layout and Simulation (Chapters 16-19), and

DRAM Circuit Design: Fundamental and High-Speed Topics

 

Grading
20% Homework and class participation
20% Quizzes
20% Mid-term test
20% Project 
20% Final

 

The CMOSedu.com Google groupís (http://groups.google.com/group/cmosedu) and the email address is CMOSedu@googlegroups.com

Email questions should be sent to the courseís Google group (not directly to the instructor).

While the instructor may likely respond quickly (to make getting the credit for the class participation challenging) questions for the instructor (only) should be asked in person during his office hours.

 

Policies

No laptops or Internet appliances can be used during lectures.

No late work accepted. All assigned work is due at the beginning of class.

Neither the final exam nor final project will be returned at the end of the semester.

Regularly being tardy for lectures, leaving in the middle of lectures, or earlier from lectures is unacceptable without prior consent of the instructor

Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)

 

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