You mention, in Ch. 22, that to improve the CMRR of a diff-amp the capacitance on the sources of the diff-pair should be
reduced. Specifically, on page 724, Fig. 22.18, you mentioned that the capacitance of the sources was minimized by having
the two MOS input transistors share a common source (area). This is done to keep the CMRR high at higher frequencies. I
asked our layout division whether we practice this but I was told that they don’t recommend it. The reason behind is because
our process project the ion beam onto the wafer at a certain angle and doing this “shared source area” layout would cause a
mismatch between the two transistors. Alan Hastings, author of The Art of Analog Layout also mentioned this ion beam
implantation issue on page 57 of the said book.
Yes, when designing analog circuits in the smaller processes you need to use a fixed size of MOSFET, when possible, and
simply adjust the number used (as discussed in Ch. 26). In general, those tricks like common-centroid layout, sharing the
source, etc., don't work for the smaller processes. See the comment here: http://cmosedu.com/cmos1/email/email27.htm.