What is the best thing to for me to focus on to improve the matching of two components?


The answer is very simple, AREA. In modern CMOS, say below the 0.25 um node where chemical mechanical

polishing (CMP) is used, the layers are very consistent (very flat). Oxides can be made with excellent uniformity.

The distance between implants is relatively small so there is little variation. What this means is that the benefits of

common-centroid techniques (see Fig. 5.29 and note the arrows indicating process gradients) or other layout tricks

like interdigitation are diminishing. The process gradients are getting better but the random sources are still present.

Very large devices still benefit from common-centroid techniques or if you are trying to get 1-2 mV mismatch at,

say, 3-sigma the use of common-centroid layout is recommended because process gradients are still present at those



Also, degradation mechanisms like NBTI really limit the best matching you can achieve over the lifetime of the part.

In some cases it can only take a few minutes of operation to shift the devices’ VTHN by, say, 5mVs. This is due to the

power law of the degradation mechanism with time even though the 10 year lifetime might be acceptable for the rest

of the part. One needs to be extra careful about asymmetric stress conditions which induce mismatch as well. You

won't likely make it out of burn-in conditions if asymmetric stress conditions are present. However, even matched

pairs that are stressed equally can still degrade at different rates particularly if they are very small devices. NBTI

degradation data is typically taken on large devices for this reason. The predictability of the degradation on small

devices requires very large samples to get the mean degradation rate. The worst case degradation on smaller devices

will actually be much worse than the NBTI characterization on large devices suggests. More work needs to be done

to understand these issues.


For additional information see:


Ben Millemon - CMOS Characterization, Modeling, and Circuit Design in the Presence of Random Local Variation, Master's

Thesis, 2012.


Saxena, S., Hess, C., Karbasi, H., Rossoni, A., Tonello, S., McNamara, P., Lucherini, S., Minehane, S., Dolainsky, C., and

Quarantelli, M., “Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies,” IEEE Transactions

on Electron Devics, Vol. 55, No. 1, January, 2008, pp. 131-144.