A high sensitivity
comparator was designed and laid out by Jake Baker in Tower's 0.6 um
CMOS
process using techniques to minimize the cells offset voltage, minimize
the
positive feedback stage's kickback to the inputs and add approximately
0.5 mV
hysteresis to minimize noise sensitivity. The cell is used to convert
sine
waves into logic signals for power line carrier communication
applications.
Below
is the cell layout.
