Phase-Locked
Loop with 560 MHz output
Below is the layout of a test PLL designed by Jake Baker during the summer of
1998 (Amkor wafer fabrication services, Boise, Idaho) for clock generation
using a .35 um process.
Return
Below is the layout of a test PLL designed by Jake Baker during the summer of
1998 (Amkor wafer fabrication services, Boise, Idaho) for clock generation
using a .35 um process.