EE
421L Digital Integrated Circuit Design - Lab 4
IV
characteristics of NMOS and PMOS devices in ON's C5 process
Pre-lab
work
We will,
in this lab and for most of the course
work, use the 3 terminal MOSFET symbols seen below.
The substrate of the NMOS (body of the NMOS) is connected to gnd and the n-well body of the
PMOS is connected to vdd.
Note the use of lowercase "gnd"
and "vdd" names
to match power and ground symbols in
NCC (layout versus schematic)
***For the cells you create in this lab, and others, use your initials
or some
other distinctive indication in the cells' names to show it's your
work.***
Again, don't use spaces or special characters in the names.
Create schematic cells that will be used for simulating the
current-voltage characterisitics
of 10/2 (3u/0.6u) NMOS and 20/2 (6u/0.6u)
PMOS.
Use Tools -> Simulation (Spice) -> Set Spice Model... to
set the models
to NMOS and PMOS.
The names of the models are seen in the model file, C5_models.txt
(save this file for simulations).
Note that the "Off-Page" nodes are Exported as D, G, and S in both
schematics.
Ensure that your report discusses how you draft these schematics.
Check, using F5, the schematics for errors and warnings (of course, fix
these
;-).
Next generate corresponding layouts for these schematics, DRC and NCC
the
layouts (show the steps in your report).
Use Tools -> Simulation (Spice) -> Set Spice Model... to
set the models
to NMOS and PMOS (as seen on the layout).
Note that below, D, G, S, and gnd
(or vdd) are exported
whereas in the schematic only D, G, and S
are exported.
Next generate simulation cells as seen below.
Notice that the schematic is an awkward view.
Discuss and give examples, in your report, of how to use an icon
representation
of the cell.
Note that the wire arcs seen below are labeled D and G, they are not
exported.
Ensure that your html lab report includes your name and email address
at the
beginning of the report (the top of the webpage).
When finished backup your work (webpages
and design
directory).