Lecture
notes and videos for EE 421 Digital Electronics and ECG 621 Digital
Integrated Circuit
Design, Fall 2017
December 11 – final exam (comprehensive), 6 to 8 PM, open book and closed notes. (A practice exam is found here.)
December 6 – lec27_ee421_ecg621.pdf and lec27_ee421_ecg621_video – review for the final
December 4 – lec26_ee421_ecg621.pdf and lec26_ee421_ecg621_video – flash memory circuit design
November 29 – lec25_ee421_ecg621.pdf and lec25_ee421_ecg621_video – design of clocked comparators for sensing
November 25 – Saturday meeting to work on projects at 2 PM, TBE-A311
November 22 – lec24_ee421_ecg621.pdf and lec24_ee421_ecg621_video – DRAM memory circuit design
November 20 – lec23_ee421_ecg621.pdf and lec23_ee421_ecg621_video – dyanmic logic gates
November 15 – lec22_ee421_ecg621.pdf and lec22_ee421_ecg621_video – delay calculation examples
November 13 – lec21_ee421_ecg621.pdf and lec21_ee421_ecg621_video – answer project questions
November 8 – lec20_ee421_ecg621.pdf and lec20_ee421_ecg621_video – clocked circuits, setup and hold times
November 6 – lec19_ee421_ecg621.pdf and lec19_ee421_ecg621_video – buffer design, delay calculations, static logic gate design
November 1 – lec18_ee421_ecg621.pdf and lec18_ee421_ecg621_video – discuss course projects and ring oscillators
October 30 – lec17_ee421_ecg621.pdf and lec17_ee421_ecg621_video – continue with the CMOS inverter
October 25 – lec16_ee421_ecg621.pdf and lec16_ee421_ecg621_video – pass and transmission gates, start the CMOS inverter
October 23 – lec15_ee421_ecg621.pdf and lec15_ee421_ecg621_video – start Ch. 10, models for digital design
October 18 – lec14_ee421_ecg621.pdf and lec14_ee421_ecg621_video – discuss course projects
October 16 – Midterm, open book and closed notes
study_session_1.pdf and study_session_1_video – study session for the midterm
midterm_review.pdf and midterm_review_video – review for the midterm exam
October 11 – lec13_ee421_ecg621.pdf and lec13_ee421_ecg621_video – subthreshold operation, on/off currents, short-channel behavior
October 9 – lec12_ee421_ecg621.pdf and lec12_ee421_ecg621_video – finish threshold voltage, body effect, MOSFET in the triode and saturation region
October 4 – lec11_ee421_ecg621.pdf and lec11_ee421_ecg621_video – strong inversion, depletion, accumulation, start threshold voltage
October 2 – lec10_ee421_ecg621.pdf and lec10_ee421_ecg621_video – using unit elements (again) for layout of resistors and capacitors, review depletion capacitance again, MOSFET oxide capacitance
September 27 – lec9_ee421_ecg621.pdf and lec9_ee421_ecg621_video – more resistor layout, laying out wide and long MOSFETs, using unit elements, common-centroid layout, matching
September 25 – lec8_ee421_ecg621.pdf and lec8_ee421_ecg621_video – more MOSFET layouts, standard cell frames, hi-res poly layer in the C5 process, poly-poly caps
September 20 – lec7_ee421_ecg621.pdf and lec7_ee421_ecg621_video – layout of a MOSFET, the active and poly layers, substrate/well contacts
September 18 – lec6_ee421_ecg621.pdf and lec6_ee421_ecg621_video – delay through the metal layers, crosstalk and ground bounce
September 13 – lec5_ee421_ecg621.pdf and lec5_ee421_ecg621_video – the metal layers, layout out a bond pad, capacitance, vias
September 11 – lec4_ee421_ecg621.pdf and lec4_ee421_ecg621_video – reverse recovery time of a forward biased diode
September 6 – lec3_ee421_ecg621.pdf and lec3_ee421_ecg621_video – depletion capacitance, RC delay through an n-well resistor
September 4 – Labor Day Recess
August 30 – lec2_ee421_ecg621.pdf and lec2_ee421_ecg621_video – making a design directory in Cadence for the C5 process, start Ch. 2, The Well
August 28 – lec1_ee421_ecg621.pdf and lec1_ee421_ecg621_video – course introduction, setting up Cadence