Lab 5 - ECE 421L 

Authored by Baylee Perera, pererb1@unlv.nevada.edu

October 11, 2023

Design, layout, and simulation of a CMOS inverter

Prelab:

The prelab consisted of going through Tutorial 3 to make a CMOS inverter. 

Schematic of inverter using NMOS and PMOS
Schematic of inverter in use. Using a handmade symbol.
Out of the inverter compared to input.
Extracted view output vs input simulation.

Lab Process:

Creating a 48u/24u Inverter:

Same process like the previous one.

12u/6u Inverter Schematic
12u/6u Inverter Symbol
12u/6u Inverter Layout
Checking that Extracted View and Schematic pass LVS

Creating a 48u/24u Inverter:

Same process like the previous one.

48u/24u Inverter Schematic
48u/24u Inverter Symbol
48u/24u Inverter Layout
Checking that Extracted View and Schematic pass LVS

Simulations of 12u/6u Inverter by driving with capacitor loads: 

This next step is to analyze how the schematic is affected by having a capacitor added on.

Capacitance Sweep:	Schematic:	Spectre Simulations	Ultrasim Simulations
100fF, 1pF, 10 pf, 100 pF

Simulations of 48u/24u Inverter by driving with capacitor loads: 

Same process like the previous one.

Capacitance:	Schematic:	Spectre Simulations	Ultrasim Simulations
100fF, 1pF, 10 pf, 100 pF

Conclusion:

When there is a higher capacitor load, the transition on the output is going to slow down. As we can also see from out lab data, the 48u/4u inverter ended up having a faster transition. This is due to it's increased size which then decreases the resistance. 

Cadence files: here

Proof of backed up lab:

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