EE
421L DIGITAL INTEGRATED CIRCUIT DESIGN
Josue Magana
Quezada
Email:
maganaqu@unlv.nevada.edu
| LAB
1
Laboratory introduction, generating/posting html lab reports,
installing and using Cadence |
| LAB
2 Design
of a 10-bit digital-to-analog converter (DAC)
|
| LAB
3 Layout
of a 10–bit DAC |
| LAB
4 IV
characteristics and layout of NMOS and PMOS devices in ON's C5 process |
| LAB
5
Design, layout, and simulation of a CMOS inverter |
| LAB
6 Design,
layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder |
| LAB
7 Using
buses and arrays in the design of word inverters, muxes, and high–speed
adders |
| LAB 8
Generating a test chip layout for fabrication
|
| Project |
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