| Name | Last modified | Size | Description | |
|---|---|---|---|---|
| Parent Directory | - | |||
| full_adder_layout.jpg | 2023-10-25 05:21 | 637K | ||
| full_adder_sim.jpg | 2023-10-25 05:21 | 488K | ||
| sim_gates.jpg | 2023-10-25 05:21 | 174K | ||
| lab6.zip | 2023-10-25 05:21 | 171K | ||
| xor_layout.jpg | 2023-10-25 05:21 | 130K | ||
| vpulse.jpg | 2023-10-25 05:21 | 85K | ||
| xor_schematic.jpg | 2023-10-25 05:21 | 84K | ||
| prelab_layout.jpg | 2023-10-25 05:21 | 64K | ||
| full_adder_schematic..> | 2023-10-25 05:21 | 55K | ||
| full_adder_LVS.jpg | 2023-10-25 05:21 | 54K | ||
| xor_LVS.jpg | 2023-10-25 05:21 | 54K | ||
| prelab_schematic.jpg | 2023-10-25 05:21 | 52K | ||
| nand_schematic.jpg | 2023-10-25 05:21 | 52K | ||
| prelab_LVS.jpg | 2023-10-25 05:21 | 50K | ||
| nand_LVS.jpg | 2023-10-25 05:21 | 50K | ||
| sim_gates_schematic.jpg | 2023-10-25 05:21 | 47K | ||
| nand_layout.jpg | 2023-10-25 05:21 | 46K | ||
| xor_DRC.jpg | 2023-10-25 05:21 | 44K | ||
| nand_DRC.jpg | 2023-10-25 05:21 | 43K | ||
| full_adder_DRC.jpg | 2023-10-25 05:21 | 43K | ||
| prelab_DRC.jpg | 2023-10-25 05:21 | 42K | ||
| lab6.htm | 2023-10-25 05:21 | 42K | ||
| backup.jpg | 2023-10-25 05:21 | 26K | ||
| full_adder_symbol.jpg | 2023-10-25 05:21 | 23K | ||
| xor_symbol.jpg | 2023-10-25 05:21 | 20K | ||
| nand_symbol.jpg | 2023-10-25 05:21 | 16K | ||
| prelab_symbol.jpg | 2023-10-25 05:21 | 14K | ||
| full_adder_sim_schem..> | 2023-10-25 05:21 | 7.4K | ||
