Lab 6 - ECE 421L 

Authored by Kanoa Hokoana, hokoana@unlv.nevada.edu

October 18, 2023

 

Lab 6: Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

 

For the prelab I went through tutorial 4.

For tutorial 4 I made a nand gate. This is the schematic for the nand gate.


I then made a symbol.


Then I made a layout for the nand gate.


DRC and LVS check


This concludes tutorial 4 and the prelab.

For the main part of the lab I drafted and simulated a 2-input NAND gate, 2-input XOR gate, and a full-adder.

  

This is the schematic for the 2-input NAND gate.


I then made the symbol for the schematic.


Then I made the layout for the 2-input NAND gate.


DRC and LVS Check



   

I then drafted the schematic for the 2-input XOR gate.


I then created a symbol for the 2-input XOR gate.


I then drafted the layout for the 2-input XOR gate.


DRC and LVS Check


 

I then simulated the gates for all possible inputs using the schematic below


I set up the vpulse to simulate a digital input.


This is the simulation.

As seen above the outputs and inputs match with the truth tables below.

   

NAND Gate

AB AnandB
001
011
101
110
    

XOR Gate

AB AxorB
000
011
101
110
 

I then drafted the schematic for a full-adder.

I then made a symbol for the full-adder.

I then drafted the layout for a full-adder.


DRC and LVS check

I then simulated the full-adder for all possible inputs using the schematic below.

This is the simulation

The simulation matches the output of the full-adder truth table below.

Full-Adder

abcin scout
000  00
001 10
010 10
011 01
100 10
101 01
110 01
111 11
   

Backing up work

 

These are the files used in this lab: lab6.zip

 

This completes lab 6.

   

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