Lab 8 - Test Chip Layout

Lab 8 - ECE 421L

Brandon Staffieri, Anthony Torres, Matthew Weishaar

staffier@unlv.nevada.edu, torrea20@unlv.nevada.edu, weishm1@unlv.nevada.edu

November 24, 2021

Lab Description

Generating a test chip layout for submission to MOSIS for fabrication

Prelab Content

Prior to this lab session, we were tasked with backing up our previous work (as usual) as well as finishing Tutorial 6, in which we learned how to place circuit layouts in a padframe for frabrication. We were also tasked with giving the entire lab document a quick read through in preparation of the actual lab.

Pad Schematic:

Pad Symbol:

Pad Layout:

Pad Frame Schematic:

Pad Frame Symbol:

Pad Frame Layout:

Postlab Report

For the main portion of the lab, our group of 3 was tasked with putting several test structures onto a chip. Each test circuit was required to have its own power pin, so that a vdd!-gnd! short in one circuit would not make any of the other circtuits inoperable; however, they did all share a common ground pin (pin 20).

The test structures required are as follows: 31-stage ring oscillator, NAND and NOR gates using 6u/0.6u NMOSs and PMOSs, inverter made with a 6u/0.6u NMOS and 12u/0.6u PMOS, transistors (both PMOS and NMOS) measuring 6u/0.6u, a voltage divider using resistors implemented using the n-well, and at least one course project.

The implementations of those components in order can be found as follows (with little commentary until the chip section as these are mostly previously drafted designs from prior labs. Additionally, all images can be clicked to enlarge):

Ring Oscillator
The ring oscillator that we are implementing in the chip will use the ring oscillator that we designed in an earlier lab along with a buffer, and it uses a modified symbol to take in a VDD input.

Ring Oscillator Schematic:

Ring Oscillator Symbol:

Ring Oscillator Layout:

Ring Oscillator DRC Clean:

Ring Oscillator Extracted:

Ring Oscillator LVS:

Buffer Schematic:

Buffer Symbol:

Buffer Layout:

Buffer DRC Clean:

Buffer Extracted:

Ring Oscillator Buffer Schematic:

Ring Oscillator Buffer Symbol:

Ring Oscillator Buffer Layout:

Ring Oscillator Buffer DRC Clean:

Ring Oscillator Buffer Extracted:

NAND Gate
NAND Schematic:

NAND Symbol:

NAND Layout:

NAND DRC Clean:

NAND Extracted:

NOR Gate
NOR Schematic:

NOR Symbol:

NOR Layout:

NOR DRC Clean:

NOR Extracted:

NOR LVS Clean:

NMOS
NMOS Schematic:

NMOS Symbol:

NMOS Layout:

NMOS DRC Clean:

NMOS Extracted:

NMOS LVS Clean:

PMOS
PMOS Schematic:

PMOS Symbol:

PMOS Layout:

PMOS DRC Clean:

PMOS Extracted:

PMOS LVS Clean:

Inverter
Inverter Schematic:

Inverter Symbol:

Inverter Layout:

Inverter DRC Clean:

Inverter Extracted:

Inverter LVS Clean:

Voltage Divider

Voltage Divider Schematic:

Voltage Divider Symbol:

10K Resistor Layout:

10K Resistor Extracted:

25K Resistor Layout:

25K Resistor Extracted:

Voltage Divider Layout:

Voltage Divider DRC Clean:

Voltage Divider Extracted:

Voltage Divider LVS Clean:

Course Project

For the course project, we implemented a design from the lecture portion of the course, being a switching power supply boost converter. This is a DC-to-DC power coverter that steps up the voltage from its input.

Course Project Schematic:

Course Project Symbol:

Course Project Layout:

Course Project DRC Clean:

Course Project Extracted:

Chip

Now for the actual chip itself, we used the pad and padframe that we created in Tutorial 6 in order to set it up. The schematic simply has all of the components with appropriate pins assigned and the layout simply shows each component placed relatively close to the pins that it utilizes, with metal layers to attach the component to either its corresponding pins or the common ground (pin 20).

As the bond pads indicate the pin assignments for the chip, testing the chip is simple, as all you have to do is SMD solder a wire to the pad and create the necessary connections to run any of the components. Pin 20 is a common ground for all of the implemented components, and each component has its own VDD pin that will need to be supplied with power in order to drive it. The pin assignments correspond to the following image, and our implementation can be observed after: