Lab 8 - EE 421L Digital Integrated Circuit Design

The Team

Damian Aceves Franco,

Email: acevesfr@unlv.nevada.edu

David Pinales

Email: pinales@unlv.nevada.edu

Ryan Eclarinal

Email: eclarina@unlv.nevada.edu

Due December 1

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Generating a test chip layout for submission to MOSIS for fabrication

Pre-lab work

• Back-up all of your work from the lab and the course.
• Go through Cadence Tutorial 6 seen here.
• Read through the lab in its entirety before starting to work on it

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Check and Save the schematic.

Use Check -> find marker to ignore the warning that the pin is floating.

Check and Save the schematic again

Create a schematic view of a cell called “chip” and add the cells we’ve created in the tutorial.

Wire the cells up as seen (an arbitrary connection).

Note how we’ve used pin<20> for ground and pin<40> for power.

We are ready to connect the cells up to the padframe in the layout.

Create of layout view of the “chip” cell.

Place the R_div, NMOS_IV, PMOS_IV, inverter, nand2, and ring oscillator cells near the pads that they will connect to

When done setting up and wiring DRC

extract the layout and LVS

Lab description

The chip should include the following test structures:

• One, or more if possible, course projects
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
• Note that only one pad is needed for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)
• Ground should be pin 20.

• Power should not be shared between the circuits so that a vdd!-gnd! short in one circuit doesn't make one of the other circuits inoperable.

  The image seen at the bottom of the page shows how the chip's pads correspond to the pins of the 40 pin DIP package we'll receive from MOSIS.

     

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DRC

                 
LVS

Layout

DRC 

LVS 

THE CHIP

Schematic 

Layout

DRC 

LVS 

PINS 

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