Lab 5 - EE 421L 

September 22 – Lab5 – Design, layout, and simulation of a CMOS inverter, due October 6 

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Pre-lab work

• Back-up all of your work from the lab and the course.
• Go through Tutorial 3 seen here.

open PMOS_IV and do the same with pmos4

                 

Wire the inverter, and add input pin A and output pin Ai

                         
Creating symbol for this inverter to use in another schematic (Create -> Cell View -> From Cell View)

                     

                   

Add metal1 pins, where A is an input, Ai is an output. DRC the layout

Extract the layout, and LVS the extracted layout

                     

Launching the ADE, and setting up the MOSFET models

                   
go to choosing analyses and to the following

                     
choose your outputs

                     

Using Graph -> Split Current Strip to see the 2 signals in 2 different graphs

                 

Rerunning the Simulator using the saved states

                 

• Draft schematics, layouts, and symbols for two inverters having sizes of: 
• 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
• 48u/24u where the devices use a multiplier, M = 4 (set along with the width and length of the MOSFET, image), as seen below 
• Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load
• Comment, in your report, on the results
• Use UltraSim (Cadence's fast SPICE simulator for larger circuits at the cost of accuracy) and repeat the above simulations 
• Use Setup -> Simulator/Directory/Host and select UltraSim as seen below
• You'll also have to point to the MOSFET models again as seen below
• Note that UltraSim only performs transient simulations (not AC, Noise, DC, operating point, etc.)  
• Not knowing this last item will lead to wasted time if trying to use UltraSim exclusively for simulations  

Make new Libary->Lab5

               

Schematic of the 12/6 PMOS-NMOS inverter

                   

Create symbol for this inverter Create -> Cell View -> From Cell View

                     

Layout the Inverter and DRC

                 

Extract the layout, and LVS the extracted layout

                 

                     
Copy experiment 1 cell and change the CDF parameters of PMOS and NMOS

layout the schematic

         

make a symbol

           

Layout the Inverter in layout and DRC then extarct it

             

Do the LVS

                   

Simulating the 12μ/6μ Inverter first, here is the following schematic

                           

Launching the ADE, adding the model libraries, and doing a transient response

                       
make sure to do the following and to add the variables

                         
load Model Libraries

                       

open Parametric Analysis with the Variable cap and input the following information

                       
press the green button

                       

Simulating the 48μ/24μ Inverter the same way we did the 12/6 Inverter




                   
             

Setup the following for ultrasim

             
Press OK