EE 421L

Fall 2020

Do Le
led2@unlv.nevada.edu

 

My Labs:

Lab 1 Lab introduction; Cadence; Editing HTML (August 26, 2020)

Lab 2 10-bit Digital-to-Analog Converter Schematic (September 2, 2020)

Lab 3 10-bit Digital-to-Analog Converter Layout (September 9, 2020)

Lab 4 NMOS and PMOS IV Characteristics; NMOS and PMOS Testpad Layout (September 16, 2020)

Lab 5 Design and Layout of Inverter (September 23, 2020)

Lab 6 Design and Layout of NAND and XOR gate; Full Adder (October 7, 2020)

Lab 7 Using Buses and Arrays, Design of Inverters, Muxes, and High-speed Adders (October 21, 2020)

Lab 8 Generating Test Chip (November 25, 2020)

  

 

 

Project Digital Receiver Circuit (November 25, 2020)

 

 

   

  

  

  

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