Lab

Lab 5 - EE421L

Authored by Rhyan Granados

9/23/20

Goal

This lab is focused on design, layout, and simulation of a CMOS inverter.

Prelab

inverter schematic	inverter symbol
inverter layout	LVS Certification

inverter in a circuit with simulation

The Lab

1) Draft 12u/6u CMOS inverter layout and schematic

schematic	layout
extracted	symbol

DRC and LVS certification:

2) Draft 48u/24u CMOS inverter layout and schematic

schematic	layout
extracted	symbol

DRC and LVS certification:

Schematic to be used for simulations:

fig21

3) Driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load with our inverter using Spectre to simulate

4) Driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load with our inverter using Ultrasim to simulate

5) Observations
It is plain to see that when input is high, our input is low. It also takes longer for the output to reach 0V when the capacitance is lower. Regarding Ultrasim and Spectre, Ultrasim has smoother curves due to it showing less detail than Spectre.

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