Lab
X - ECE 421L
Authored
by Ryan Castellano,
October 21, 2020
Lab
description
In this lab, I'll be designing and simulating some basic logic circuits.
Prelab:
In the prelab, I worked on tutorial 4. I first created the schematic of the NAND gate and created its symbol as shown:
![](Screenshot%20%28365%29.png)
![](Screenshot%20%28366%29.png)
Next, I created the simulator schematic and ran it for the following results:
![](Screenshot%20%28367%29.png)
![](Screenshot%20%28368%29.png)
I did the layout next and extracted so I could get the LVS:
![](Screenshot%20%28369%29.png)
![](Screenshot%20%28370%29.png)
Finally, I changed the LVS rules to get the following error message:
![](Screenshot%20%28371%29.png)
Lab Main Content:
Since the NAND gate was done in the prelab portion, this section will focus strictly on the XOR and the full adder.
XOR Schematic and Symbol:
![](Screenshot%20%28375%29.png)
![](Screenshot%20%28376%29.png)
XOR simulator circuit with results:
![](Screenshot%20%28378%29.png)
![](Screenshot%20%28377%29.png)
As you can see, the output is high when the inputs are opposites, proving the XOR works.
Layout, DRC, and LVS:
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