salazs3 lab6

Lab 6 - EE 421L

Authored by Steve Salazar Rivas

Email: salazs3@unlv.nevada.edu

October 23, 2019

Prelab: For lab 6, we went through Tutorial 4 in order to draw the schematic, layout, and corresponding symbol of a CMOS NAND gate. We will use this CMOS NAND gate along with its corresponding schematic, layout, and symbol for the actual lab 6.

Actual Lab 6:

Below, we have the schematic for our CMOS NAND gate.

Here is the corresponding layout for our NAND gate...

Our layout underwent DRC nicely...

This is the corresponding symbol for our NAND gate...

This is the extracted view of our NAND gate...

Our net-lists matched after LVS, but we paid special attention with the mismatched parameters after allowing "compare FET parameters"...

Here is the simulation schematic used for our NAND gate...

Here are the simulation results of our NAND gate

Below is the schematic for our XOR gate....

This is the corresponding XOR symbol...

Below is our XOR layout...

Our XOR layout under DRC nicely...

Here is the verification that our extracted view undergoes LVS very well...

We can see the LVS window for the XOR layout below...

The net-lists match successfully...

Below is the simulation schematic used to see how all of our gates work...

Here is our simulation results. After analyzing the results, we can see that the pulse signals that we have for our inputs create glitches at our rise/fall instances. This small yet important delay can point to having one gate having to delay outputting a correct signal before having another gate that is connected to this gate output another correct signal after a delay. This results in our glitches for our minute yet important to note glitches in our outputs.