EE 421L - Lab 7

Lab 7 - ECE 421L

Authored by Geovanni Portillo,

November 1st, 2019

Using buses and arrays in the design of word inverters, muxes, and high-speed adders

All images can be double-clicked for larger versions

Prelab:

Back-up all of your work from the lab and the course.

No additional work done between when I finished lab 6 up through now, so the same backup will be used

Go through Tutorial 5 seen here.

Tutorial 5 goes through the process of designing a ring oscillator and simulating it

Ring Oscillator
Schematic	Symbol

Layout	Extracted

Sim Schematic	Sim Plot

Read through the entire lab before starting it.

Lab:

Make an equivalent, more concise, schematic by instantiating an inverter and naming the inverter using an arrayed name (I0<3:0>).

Connect a wide-wire (bus) and connect it to input and output pins. Create a symbol for the schematic.

Schematic	Symbol

Using this symbol create a simulation schematic.
All four inverters' inputs are tied together to an input pulse source.

The out<0> is not connected to a load while out<3> is connected to a 100fF load.

The out<1> is connected to a 1 pF load while out<2> is connected to a 500 fF load.

Schematic	Plot

Being that the delay and rise/fall times rely on the time constant RC, we can see that as we increase the capacitor load from 0 to 1pF the time constant increasesand so do the delays and the rise/fall times.

Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.

	Schematics	Symbols
NAND
NOR
AND
INVERTER
OR

Provide a few simulation examples using these gates.

	Schematics	Plots
NAND
NOR
AND
INVERTER
OR

Next examine the schematic of a 2-to-1 DEMUX/MUX (and the symbol).
Simulate the operation of this circuit using Spectre and explain how it works.

MUX/DEMUX
Schematic	Symbol

MUX Simulation Schematic	Plot

DEMUX Simulation Schematic	Plot

As seen in the MUX plot, when S is set to '0', the output becomes that of the B input and when S is set to '1' the output is becomes that of the A input.

And in the DEMUX plot we see that when S is '1' B takes the signal of Z, though A remains '1' at this time. Then when S is '0', A takes the signal ofZ.

Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
Include an inverter in your design so the cell only needs one select input, S (the complement, Si, is generated using an inverter).
Use simulations to verify the operation of your design.

8-bit MUX/DEMUX
Schematic	Symbol

Simulation
Schematic	Plot

A<7:0> is set to '1111 0000' and B<7:0> is set to '0000 1111' and when S is set to '0', Z<7:0> is set to B<7:0>. And when S is set to '1', Z<7:0> equals A<7:0>

Finally, draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
Create an adder symbol for this circuit.

Full-adder
Schematic	Symbol

Layout	Extraction

DRC	LVS

Use this symbol to draft an 8-bit adder schematic and symbol.
Lay out this 8-bit adder cell.
Show that your layout DRCs and LVSs correctly.

8-bit Full-Adder
Schematic	Symbol

Layout	Extraction

DRC	LVS

Simulate the operation of your 8-bit adder.

Schematic	Plot

In the above schematic, when A or B are high or low they will have an 8-bit value such as '1111 1111' and '0000 0000', When Cn is high, we can see that the sum (Sn<0:7>) is '0000 0001'. And when A or B are high and nothing else, the sum is '1111 1111'. Then when A and Cn are high or B and Cn are high, the sum is then

'0000 0000' and Cout(Cnplus1<7>) is '1'. When A and B are high but not Cn, the sum is '1111 1110' and Cout is '1'. When A, B and Cn are high, the sum is '1111 1111' and Cout is '1'.

End of lab Backup

Return to Index

Return to EE 421 Labs