Lab Final Project

Lab Project - EE 421L

Authored by Martin Jaime,

email: jaimem5 at the UNLV students domain

Date November 30, 2016

Objective:

Design a circuit that takes a serial input and detects (outputs a high logic signal called detect) the sequence 101011
The inputs to your circuit are clk and in
Make sure that the output of your design, detect, is buffered before connecting to a pad

Project Lab Report
Conceptually, the detector circuit consists of a clocked 6-bit shift register that will serially read a sequence, and compare it to the expected value. Since the register records the data in D flip-flops, we can check the sequence by

detect = A*B'*C*D'*E*F

Therefore, the output of the register should be ANDed together into a six input AND gate. Fortunately, D flip-flops have complementary outputs, so no additional inverters are required. The output of the AND gate will be a logic '1' when the shift register contains the logic value '101011'. The following is the schematic used for the sequence detector illustrated with logic gates.

Schematic of sequence detector.

Modules:

The 6 input NAND gate was designed as the NAND gate is commonly implemented, with additional inputs, and an inverter at the output. Note that the schematic was wired with arrayed nets for simplicity.

	A detailed image of the layout is found here.

D Flip-Flop

	A detailed image of the layout is found here.
	The flip-flop reads in the input value at the rising edge of the clock.

Transmission gate

	A detailed image of the layout is found here.
	Note that the output of the gate only matches the input when the transistors are enabled on net3 and net4.

Buffer to output to a 20pF load is necessary. The following buffer serves that purpose.

The complete layout is difficult to see in an image, but here is a close up.

Testing the sequence detecting circuit

	Input sequence: 0101011100. The output of the detecting circuit is only high when the register's value is 101011.

All backed up work can be found at https://github.com/martinjaime/CMOSedu-Reports

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