Lab 7: Using Busses and Arrays in the Desing of Word Inverters, Muxes, and High-Speed Adders - EE 421L     

Authored By: Joey Yurgelon

Email: yurgelon@unlv.nevada.edu

October 21st, 2015

Pre-lab Work:

• Back-up all of your work from the lab and the course.
• Go through Tutorial 5 seen here.
• Read through the entire lab before starting it.

• Students will learn to use busses and array instances to make schematic, testing, and layout easier.

• Show, in your lab report, how a capacitive load influences the delay and rise/fall times of the inverter array.

• Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.
• Provide a few simulation examples using these gates.

• Next examine the following schematic.
• This is the schematic of a 2-to-1 DEMUX/MUX (and the symbol).
• Simulate the operation of this circuit using Spectre and explain how it works. 
• Make sure to show, using simulations, how the circuit can be used for both multiplexing and de-multiplexing.  

• Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
• Include an inverter in your design so the cell only needs one select input, S (the complement, Si, is generated using an inverter).
• Use simulations to verify the operation of your design.

• Finally, draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS). 
• Create an adder symbol for this circuit (see the symbol used in lab6).
• Use this symbol to draft an 8-bit adder schematic and symbol.
• Simulate the operation of your 8-bit adder.
• Lay out this 8-bit adder cell (*note* that this is the only layout required in this lab).
• Show that your layout DRCs and LVSs correctly. 

• ALL OF THE DESIGN FILES ASSOCIATED WITH THIS LAB CAN BE FOUND HERE.

Experimental Results: 

    Exercise #1: Show, in your lab report, how a capacitive load influences the delay and rise/fall times of the inverter array.

• One can see below that by increasing the capacitive load on the output of the inverter, there are significant effects to the device's rise/fall times and delay. This is due to the inverter not being able to supply the necessary current to charge the capacitor fast enough.

• I was able to create the schematics for each of the following gates, and then convert them into 8-bit word versions by using arrayed instances with bus connections. The symbols for each of the devices can be seen below along with a simulation of their operation. Two simulations are shown below, one with a capacitive load of 100 fF and the other with 1 pF. 

Gates Driven with a 100fF Capacitive Load
Gates Driven with a 1pF Capacitive Load

 Exercise #3: Draft the schematic of a 2-to-1 DEMUX/MUX and explain how it works in both configurations using spectre. Create an 8-bit wide version with only a single 'Select' input. 

• Below one can see the 2-to-1 DEMUX/MUX with and without the single 'Select' input. To create a single 'Select' line, I simply put in an inverter instance into the schematic to flip the 'S' bit automatically. I created two different symbols to show the difference. 
• The MUX takes in inputs A and B. Only one of these inputs is connected to the output, Z, at any given time. To decide which input (A or B) is connected, we use the 'Select' or S input. If S is high, we connect the A input to the output, and if S is low, we connect the B input to the output. Since this device may be used as a DEMUX as well, the operation is completely reversed. In this instance, we take the single input which is now Z, and connect it to either output A or B. This is done by the same select line S. If S is high then Z is connected to A, and if S is low then Z is connected to B. Using the simulations below, we can see that this is indeed the case. Random pulses were used to show a variety of scenarios.
• As for the DEMUX operation, the same operation takes place. The difference between the MUX/DEMUX is the amount of avaialble inputs and outputs. In either case, however, the output is simply being connected to the input by opening or closing a certain transmission gate.

 Exercise #4: Draft the full-adder schematic seen in Fig. 12.20. Layout, simulate, and produce a 8-bit adder cell. 

• This full-adder does away with the direct logic implementation that was used in the previous lab. In this case, we are using pass logic which allows for the overall design to be far more streamlined than before. This allows us to operate the circuit at a much faster rate. There were few issues with laying out the device, and creating an 8-bit version. A few missing connections halted the LVS, but I was able to run through the output log and correct the issue. As one may see below, the layout for the single bit and 8-bit versions were both DRC and LVS clean. Simulations can be seen below to verify the operation of the circuit in either version. For the 8-bit version, however, the addition scheme is as follows: A (11111111) + B (00000000) + Cin (1) = Cout<7>, S<0:7> (100000000).

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