EE 421L Digital Electronics Lab #2

Authored by Jonathan Young on September 14, 2015
Email: youngj1ATunlv.nevada.edu

Lab Topics:

Design of a 10-bit digital-to-analog converter (DAC).

Lab Description:

Pre-Lab:

1. Provide a narrative of the steps seen in Lab 2 directions.
2. Provide and discuss cadence simulation results, which are different from those illustrated in the Lab 2 directions to demonstrate understanding of the ADC and DAC.
3. Explain how to determine the least significant bit (LSB, the minimum voltage change on the ADC's input to see a change in the digital code B[9:0]) of the converter. Use simulations to back up answer.

Narrative:

Download the lab2.zip file and extract it to to Cadence for use in this lab. The following images will demonstrate this process.

Contents of Lab2.zip
Figure 1: This screen capture shows the contents of the Lab2.zip file. The lab2 folder is what will be copied (extracted) into the CMOSedu folder.
Extracting Lab2 folder to CMOSedu
Figure 2: This screen capture shows the lab2 folder being successful extracted into the CMOSedu folder located on the Cadence server.
Defining Lab2 folder for Cadence
Figure 3: This screen capture shows the modification of the cds.lib file, which will add the recently extracted lab2 folder to the Cadence library. The following line will be added to the bottom of this text file: DEFINE lab2 $HOME/CMOSedu/lab2
Showing Cadence Library with Lab2
Figure 4: This screen capture shows the lab2 folder in the Cadence (Tools>Library Manager). This specifically allows us to view the lab2 schematic and simulations in Cadence, which was already done for us. This is why extracting the lab2 folder to CMOSedu was useful.
Loading Simulation with Load Session
Figure 5: Now that the schematic is loaded, we want to load the simulation provided in the lab2 folder. To do this, we click Launch>ADE L. This will bring up the Analog Design Environment for simulations.
An iamge of loading sessions and running simulations
Figure 6: This screen capture shows the using the simulation window (left), which is ran by pressing the green button, to generate the schematic simulation (right). Note: The state is loaded by clicking Session>Load State, as this simulation was already done for us, thus it just needed to be loaded.
Final simulation showing background and trace color changes
Figure 7: This is the final modified simulation. To change the background color, right click on the graph and select 'graph properties'. Once inside this window, click the black box and change to any color one prefers. To change the trace colors, line thickness, and/or styles, right click on the individual trace and select properties. This will bring up a window, allowing all of the previously mentioned settings to be changed at once.

Concept & Simulation Differences:

The general concept of the Analog to Digital Converter (ADC) is to convert the input voltage (sin wave, in this case) to a digital output. This output is then sent as B[9:0] to the Digital to Analog Converter (DAC), which in turns generates an analog output (its best representation of the sine wave, but is a very small step function that closely corresponds to a sin wave). This is seen in Figure 7, above.

Varying of the input voltages that exceed the acceptable range or are negative will affect what the ADC and DAC will handle. Thus, since our convert only handles 0V to 5V, anything outside of this specific range will result in the DAC having a steady straight line at the corresponding voltage line. Example, as seen below: When the input voltage is at 6 Volts, the DAC only outputs 5V as its max and remains a steady flat line. This is because the 6V is outside the range of the convert by 1V. Thus, the simulation above in Figure 7 is different than below as the DAC does not closely follow the input sin wave.

Image displaying limitations of circuit
Figure 8: This screen capture shows what happens when the input is changed from 2.5V offset and 2.5V input to 0V offset and 6V input. Note: The negative values for the input (green trace) has a corresponding flat output line of 0 V (red trace). This is because our converter cannot handle negative voltages. As for the cutoff at 5V, this is because our converter can only handle up to 5V. Anything greater than this (green trace above) will have a corresponding flat line (steady voltage, red trace above).

Least Significant Bit Determination:

The least significant bit is the smallest bit value that is handled by a circuit, such as our converter above being B[0]. Anytime the input changes, it causes a corresponding output which affects this value. This is controlled by voltage values. In this case we need to know the smallest amount of voltage value that will affect this output bit, which is determined by the following: 1/(2^(10))=1/1024. Note: This is a fraction, which corresponds to 1 bit over the total number of bits, since a bit can be on or off this is binary (2). To determine the voltage, we take the fraction of all the bits and multiply by the maximum input voltage the circuit accepts (5 in this case), which gives us the following: 5/1024= 0.0048828125. This value is the smallest voltage value that will cause a change in a single bit, thus anything around 5mV will see B[0] output a value of 1.

A side note, to change the first and second values to 1, B[1:0], 00000011, the following voltage will need to be applied: 5/1024 * (1+2)= 0.0146484375, which is roughly 14.6mV.

Post Lab:

1. Design a 10-bit DAC using n-well R of 10k resistors, using the resistor topology from the CMOS textbook. For the 2R resistors, use two separate 10k resistors in series. For R, use a single 10k resistor.
2. Discuss how to find the output resistance of the 10-bit DAC, with the final result being R by combining resistors in parallels and series.
3. Drive a load on the 10-bit DAC. Ground all inputs, except for B9, which connects a pulse input. Show and calculate the delay through the 10-bit DAC with a 10pF capacitor load. Verify the simulation matches calculations.
4. Create a symbol view of the 10-bit DAC, using a copy of the 10-bit DAC provided in the lab2.zip download. The only changes that need to be made are with the schematic. Simulate and verify that the 10-bit resistor topology DAC functions correctly.
5. Create new schematics and simulations to test the load of a resistor, capacitor, and both in parallel. Explain what happens with the resistor load, specifically related to voltage.
6. Discuss what happens if the resistance of the switches is not small compared to R.
7. Back up your work.

Circuit Design:

For this lab, we are going to be using resistors to create a DAC unit. The DAC should function similar to that in the Pre-Lab. To accomplish this tasks, the use of 10k resistors will be used for every instance of R and two 10k resistors will be in series will be used for every instance of 2R in the schematic below. Once this is accomplished, a symbol will be created reflecting these resistors. This symbol will then be used to place the resistors as our DAC unit, with a new symbol being created to reflect this. We will directly tie the input pins (b0..b9), b9 being the most significant bit, into the resistor network. In the resistor based DAC design, the VDD as shown below in Figure 9 will not be used. The last 2R resistor will be tied to ground, note this will be a 20k resistor since two 10k resistors are in series.

10-bit Resistor DAC topology
Figure 9:This image shows how our resistor DAC will be constructed. The CL and RL will be used in later simulations to further understand the impact of our DAC and how it handles various loads.
Schematic of 2R and R resistors
Figure 10:This image shows the schematic of the 2R and R resistors. As a reminder, the 2R resistor is created by putting two 10k resistors in series. The top/bottom pins are used for input/output, ideally to allow us to chain them in the circuit to generate the 10-bit DAC.
2R and R Symbol
Figure 11:This image shows the use of the symbol created in Figure 10 (directly from the schematic) to construct a 10-bit resistor DAC. The use of this symbol, allowed this schematic to be laid out with ease and recognition as to how the components similar to that of Figure 9.

The resistors at the bottom of Figure 11 are calculated via joining the resistors in series and in parallel. This process keeps repeating from the bottom of Figure 9 to the top of Figure 9 until the final total resistance is just R. This resistant (R) is what is added to the bottom right of Figure 11, ie the connection to ground. Note: The calculation for the 2R resistors in parallel is as follows:

Resistor Calculation

This process is demonstrated below:

Combination of Resistors
Figure 12:This image shows the process of parallel/series combination to get the single R resistance.
10-bit DAC Schematic
Figure 13:This image shows the schematic of the 10-bit DAC designed above as well as linking it together with the Analog to Digital Converter (ADC).
Simulation of 10-bit DAC Schematic
Figure 14:This image shows the simulation of the 10-bit resistor DAC. The extra straight lines in the simulation are due to convergence issues, thus changing the simulation output to be less accurate results in this simulation. In all, this simulation is similar to that in the pre-lab.
10-bit DAC with Capacitive Load
Figure 15:This image shows the schematic of the 10-bit resistor DAC, with pins [B0..B8] tied to ground, B9 tied to a pulse source, and the output with a 10pF capacitor connected to ground.

Using the schematic from Figure 15, the B9 point outputs a binary output 2 to the power of 9 (since is is in 10th place) which is 512. The voltage output from the 10-bit DAC is 5V(Vin) * (512/1024)=2.5V. The delay for this circuit is given by td=0.7RC=0.7*10kohm*10pF=70ns. Note: This delay is the half-way point of the output and thus the output at 70ns should be 2.5V/2=1.25V.

Simulation of Capacitive Load
Figure 16:This image shows the simulation of Figure 15, with the expected half-way point at 1.25V being 70ns.
Schematic with 10k Load
Figure 17:This image is a schematic with a 10k resistor load on the output of that seen in Figure 13.
Simulation of 10k Load
Figure 18:This image shows the simulation of the schematic in Figure 17. The output is clearly shown around 2.5V. The reason for this is that the 10k load resistor is in series with the 10k resistance total of the 10-bit DAC, thus creating a voltage divider which takes the original output of Figure 14 and cuts it in half.
Schematic with 10pF Capacitor Load
Figure 19:This image is a schematic with a 10pF capacitor load on the output of that seen in Figure 13.
Simulation of 10pF Capacitor Load
Figure 20:This image shows the simulation of Figure 19. The output is delayed slightly, smoother (no jagged rises and falls), and slightly reduced. The reason for the smoothness is due to the voltage rising in the capacitor and the reduction occurs due to the impedance of the capacitor.
Schematic with 10k and 10pF Load
Figure 21:This image is a schematic with a 10k resistor and a 10pF capacitor in load in parallel on the output of that seen in Figure 13.
Simulation of 10k and 10pF Load
Figure 22:This image is the simulation of the schematic in Figure 21 and is similar to the simulation of Figure 20. The only difference here is that the output is reduced by 2 because of the resistor, as discussed in Figure 18.

Discussion Question:

Prompt: In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs). Discuss what happens if the resistance of the switches isn't small compared to R.

The resistance of the switches in the circuit must be small compared to R, otherwise the switch resistance would affect the R/2R ladder network. In other words, if the switch resistance is too large it would become a resistor in series with the 2R input and thus change 2R to 2R plus switch resistance. This would affect the scaling and LSB of the 10-bit DAC.

Back Up:

Image of backing up files
Figure 23:This image shows the lab web directory and cadence directory being copied to my local lab folder on my Macintosh, which will also be backed up using Time Machine automatically.