Lab 6 - EE 421L Digital Integrated Circuit Design

Author: Matthew Meza

Email: mezam11@unlv.nevada.edu
October 19, 2015

  

Design, layout, and simulation of a CMOS Nand gate, XOR gate, and Full-Adder!


 Pre-lab work

Proof of Prelab
Schematic of NAND gate
Layout of Nand Gate
Symbol used for nand gate!

Lab Description
In this lab we will design, layout, and simulate an inverter made of NMOS and PMOS MOSFETs in ON's C5 Process. After the layout, we will plot characterization curves with different loads!

Lab Requirement

Post-Lab Excercises

                                                                                              2-Input Nand-Gate 6u/0.6u
Schematic with size of 6u/0.6u

Notice the size difference from the Pre-Lab

Layout of the Nand-Gate

Notice the size difference from the Pre-Lab
Proof of  DRC/LVS

Symbol for NAND Gate



                                                                           2-Input XOR gate using 6u/0.6u
XOR gate Schematic



Layout

XOR DRC and LVS

XOR Symbol
 
 
 
                                                        Simulations of gates!
Schematic of logic's being simulated




Inverter Sim-Logic


NAND Sim-Logic
XOR Sim-Logic
Notice how the NAND and XOR sim logic have glitches on the switching points. This is because these gates are
not ideal and have internal time delays. The internal time delays cause the output to begin to change and then return to its correct state.
 
 
 
                           Full Adder Schematic, Layout, Symbol, and Simulation


                                                        Schematic!


                                                                                                 Layout!
 Notice the gnd and vdd rails at the top and bottom of the layout, they extend the full length of the layout. Also notice how all the routing
is done on the metal 1 and metal 2 layers.

                                                                                Proof of DRC and LVS!
                  
                                                      

                                    Simulations of the Full-Adder can be seen above in the Sim-Logic section!


 
Notice the glitches at the output /s and /cout. This is because these gates are not ideal and have internal time delays. The internal time delays cause the output to begin to change and then return to its correct state.
 
 
 
       

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