Lab 5 - EE 421L Digital Integrated Circuit Design

Author: Matthew Meza

Email: mezam11@unlv.nevada.edu
September 28, 2015

  

Design, layout, and simulation of a CMOS inverter!


 Pre-lab work

Lab Description
In this lab we will design, layout, and simulate an inverter made of NMOS and PMOS MOSFETs in ON's C5 Process. After the layout, we will plot characterization curves with different loads!

Lab Requirement

Post-Lab Excercises

 

                                                                                        Inverter Circuits
Inverter1, M=1

Inverter2, M=4 (four devices in parallel)




                                                                                        Inverter1 12u/6u!
Inverter1 Schematic, DRC, LVS

Inverter1 Layout

 
 
 
                                                        Inverter2 48u/24u!
Inverter2 Schematic, DRC, LVS



Inverter2 Layout

 
 
 
 
                                          Capacitave Load Simulations
                   Inverter 1 (blue output)                                  Inverter 2 (red output)

100fF load; Blue - output!

100fF load; Red - output!

1pF load; notice the RC behavior.

1pF load; the larger MOSFETS are able to supply more
current than the smaller MOSFETS in
Inverter 1

10pF; the inverter is no longer able to supply
sufficient current.

10pF load; notice the RC behavior, the inverter
not able to supply enough current fast enough.

100pF; the inverter is completely useless at this load.

100pF; the inverter is no longer able to supply
sufficient current.
 
  The same simulations were made using UltraSim. The simulations were exactly the same as the simulations as above but nonetheless can
be found here. The complete Cadence files can be found here.
 
                                                                                                 
 

       

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