Lab 4 - EE 421L Digital Integrated Circuit Design

Author: Matthew Meza

Email: mezam11@unlv.nevada.edu
September 21, 2015

  

IV characteristics and layout of NMOS and PMOS
devices in ON's C5 process!


 Pre-lab work

Lab Description
In this lab we will layout an NMOS and PMOS MOSFET in ON's C5 Process. After the layout, we will plot characterization
curves with different parameters! Layouts will include a probe/bond pand!


Lab Requirement

Post-Lab Excercises

                                                                                                NMOS Device!

Layout of the NMOS Device. Notice the four bond-pands (big squares)
The layout DRCs just fine!

A close up of the layout. Shown is the NMOS device with
metal1 connected!


Schematic of the NMOS for simulation!
Parameters may change depending on the simulation.



The layout and schematic netlists match!
Ready for simulation!
 
 
 
                                                                                                    PMOS Device!
 
Layout of the PMOS Device. Notice the four bond-pands (big squares)
The layout DRCs just fine!


A close up of the layout. Shown is the PMOS device with
metal1 connected!

Schematic of the PMOS for simulation!
Parameters may change depending on the simulation.




The layout and schematic netlists match!
Ready for simulation!

 
 
                                                                    Simulations!

NMOS: ID vs VDS with VGS increments!

NMOS: ID vs VGS with VDS = 0.1 volts

PMOS: ID vs VSD with VSG increments!
Notice how the waveform is flipped! This is because the
plot is displaying the current flowing INTO the drain!

PMOS: ID vs VSG with VDS = 0.1 volts
Notice how the waveform is flipped! Thisis because the
plot is displaying the current flowing INTO the drain!

 
 

       

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