Lab 3 - ECE 421L
See the EE421L webpage here

Authored by Juan Buendia
buendiaj@unlv.nevada.edu
September 20, 2015

Objective: Layout of a 10-bit digital-to-analog converter (DAC)

The circuit will be based on the following DAC schematic, but will use nwell resistors.
DAC Regular Schematic
The equivalent resistance is R given by the following.
Equivalent Ressitance

The least significant bit is about 4.88 mV.
lsb
The layout
layout

The final step is to back the lab 3 file
zipfile
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