Lab 2 - ECE 421L
See the EE421L webpage here

Authored by Juan Buendia
buendiaj@unlv.nevada.edu
August 30, 2015

Objective - Design of a 10-bit digital-to-analog converter (DAC)

Prelab - Understand how an analog to digital (ADC) and a digital to analog (DAC) work

We downloaded the lab2 zip file and extracted it onto our CMOSedu directory on Mobaxterm.
 

 

 
After running Cacence, we opened an ideal ADC and DAC (sim_ideal-ADC_DAC) from the lab2 library in the library manager.
  


We ran a simulation using spectre from the ADE L menu and got the following result:
 

 
The period of the the sample clock is 10ns.
This corresponds to 1/50 of the period of the input (the period is 500ns).
Each clock inpulse samples when the input changes in phase by 7.2 degrees.
Therefore, each bit changes every time the input changes in phase by 7.2 degrees.
If we use the formula, V_out=sin(ωt + n7.2), where n is the nth sample clock, we can predict what voltage corresponds to which digital output (on B0:9).

The minimum voltage change that would create a change in the digital output on B0:9 is approx. 0.15626V. and it will give an output of approximately 2.65625V.
 


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