Lab 4 - EE 421L

Authored by Nick Repetti

repettin@unlv.nevada.edu

10/6/2014

Lab Description:

This lab will go over the simulation and layout of NMOS and PMOS devices. The lab begins with completing Tutorial 2 seen here.

Lab Report:

To begin we will simulate a 3-terminal NMOS device as seen below:



Below is the schematic for the circuit we will be simulating:



The simulation results can be found below:



Next we will design the 4-terminal NMOS device:



The schematic can be seen below:



Next is the simulation of the 4-terminal PMOS device which can be found below:



The schematic of this 4-terminal PMOS is the following:



Finally the simulation of the 4-terminal PMOS device is found below:



The rest of this lab is incomplete.

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